Abstract: The present invention is directed to methods and systems for implementing a DMA scheduling mechanism and a DMA system for transmission from fragmented buffers. According to an aspect of the present invention, a processor controls several devices via a polled interface to interleave DMA data transfers on different Input/Output (I/O) ports in an efficient manner. According to another aspect of the present invention, a system for handling transmission of network packets which are assembled from multiple memory buffers with different octet alignments is provided. The hardware/software combination allows efficient joining of packet fragments with differing octet alignments when the underlying memory system is word based, and further allows insertion of other data fields generated by a processor.

Abstract: A method and apparatus for scheduling the transmission of cells onto an network, or other packet switching network, is disclosed. The central feature of the scheduling mechanism is a quality of service engine (QoS Engine) which accelerates the processing of packets in a packet switching networks, such as an ATM network, by assisting the accurate pacing of many ATM virtual circuits. The QoS Engine allows the concurrent support of a wide variety of port speeds, traffic classes using different priorities and traffic parameters. quality of service engine (QoS Engine) works in conjunction with a network processor (NP) to allow it to maintain software flexibility, and for it to achieve accurate pacing.

Abstract: The method and apparatus correct for byte misalignment in a block of data. Switch means are set to perform a switching cycle depending on the amount of byte misalignment. Each word in the block is then transferred in accordance with the switching cycle, so that the bytes are aligned by the transfer, the aligned bytes then being stored. A first word in the data block is transferred into an input register where the amount of byte misalignment is determined in order to control the switching cycle, i.e. when the words are transferred to an output register. Also disclosed is a method of translating the encapsulation of a protocol labeled data block by removing an original header and original trailer from the data block, providing a new header and a new trailer and using the byte alignment method to determine any byte misalignment in the new header or trailer.

Abstract: A DMA scheduling mechanism for transmission of fragmented buffers having a processor for controlling several devices via a polled interface to interleave DMA data transfers on different Input/Output (I/O) ports in an efficient manner. The system handles transmission of network packets which are reassembled from multiple memory buffers with different octet alignments is provided. The hardware/software combination allows efficient joining of packet fragments with differing octet alignments when the underlying memory system is word based, and further allows insertion of other data fields generated by a processor.

Abstract: A method and apparatus for scheduling the transmission of cells onto an network, or other packet switching network, is disclosed. The central feature of the scheduling mechanism is a quality of service engine (QoS Engine) which accelerates the processing of packets in a packet switching networks, such as an ATM network, by assisting the accurate pacing of many ATM virtual circuits. The QoS Engine allows the concurrent support of a wide variety of port speeds, traffic classes using different priorities and traffic parameters. quality of service engine (QoS Engine) works in conjunction with a network processor (NP) to allow it to maintain software flexibility, and for it to achieve accurate pacing.

Abstract: A co-processor for a DSP adapted for use with a DMT communication system. The co-processor includes a decoder for converting an input stream of QAM coordinated pairs into variable length sequences of bits and a combiner having a data register and an offset register for performing a cycle in which variable length bit sequences from the decoder are assembled into a block of data having a predetermined number of fixed length data words. An output buffer is provided for writing the data words into memory, whereby the data register can be preloaded with a part of a data word in memory, the offset register being set accordingly and the address register being set to the word-aligned address of the data word in memory, so that received data can be stored at a non-word aligned address.