Patents by Inventor David Modrie

David Modrie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7263049
    Abstract: A receiver is described for delivering a data sequence (ak) at a data rate 1/T from an analog signal (Sa), the receiver comprising: a) converting means (40) for generating a received sequence (rn) by sampling the analog signal (Sa) with a sample rate of 1/Ts, whereby the sample rate 1/Ts of the received sequence (rn) is controllable by a preset value (Pv); b) digital processing means (12) for delivering a processed sequence (yn) by processing the received sequence (rn); c) a first sample rate converter (13) converting the processed sequence (yn) into an equivalent processed sequence (ye) at the data rate 1/T, whereby the data rate of the equivalent processed sequence (ye) is controllable by a control signal (Sc); d) an error generator (14) for delivering an error sequence (ek) from the equivalent processed sequence (ye); e) a control signal generating means (15) for generating the control signal (Sc) dependent on the error sequence (ek); f) a detector (16) for deriving the data sequence (ak) from the equivale
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: August 28, 2007
    Assignee: Koninklijke Philips Electronics N. V.
    Inventors: David Modrie, Koen Vanhoof, Aalbert Stek
  • Patent number: 7248630
    Abstract: The invention relates to an LMS-based asynchronous receiver for digital transmission and recording systems. The receiver comprises a digital adaptive equalizer (EQ) for receiving a received sequence rn and for delivering an equalized sequence yn. The equalizer (EQ) operates at the sampling rate 1/Ts, asynchronous to the data rate 1/T. An equalizer adaptation method using LMS techniques is described for adapting equalizer taps asynchronously to the data rate via a control loop. A first sampling rate converter (SRC1) performs timing recovery at the data rate 1/T after equalization on the equalized sequence yn. A second sampling rate converter (SRC2) is provided for converting a delayed version of the received sequence rn into an intermediate control sequence ik at the data rate 1/T.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: July 24, 2007
    Assignee: Koninklijke Philips Electronics N. V.
    Inventors: David Modrie, Rob Otte
  • Patent number: 7218581
    Abstract: A device for delivering a data signal at a data rate has crosstalk cancellation. The crosstalk reducing unit (14) has an adaptive filter (15) to generate a crosstalk signal corresponding to a track adjacent to a track being scanned. A subtractor (16) subtracts the crosstalk signal from a read signal. A calculating unit (17) calculates filter coefficients for the adaptive filter. The adaptive filter (15) and subtractor (16) are coupled to an asynchronous clock (18) for operating at an asynchronous sample rate. The crosstalk reducing unit (14) has a sample rate converter (19) coupled to a synchronous clock for converting the output of the subtractor to the data signal (8) at a synchronous sample rate. A timing recovery unit (11) is coupled to the data signal (8) for retrieving the synchronous clock corresponding to the data rate.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: May 15, 2007
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Jo Stefan Frisson, David Modrie
  • Publication number: 20070053261
    Abstract: A device for delivering a data signal at a data rate has crosstalk cancellation. The crosstalk reducing unit (14) has an adaptive filter (15) to generate a crosstalk signal corresponding to a track adjacent to a track being scanned. A subtractor (16) subtracts the crosstalk signal from a read signal. A calculating unit (17) calculates filter coefficients for the adaptive filter. The adaptive filter (15) and subtractor (16) are coupled to an asynchronous clock (18) for operating at an asynchronous sample rate. The crosstalk reducing unit (14) has a sample rate converter (19) coupled to a synchronous clock for converting the output of the subtractor to the data signal (8) at a synchronous sample rate. A timing recovery unit (11) is coupled to the data signal (8) for retrieving the synchronous clock corresponding to the data rate.
    Type: Application
    Filed: December 2, 2003
    Publication date: March 8, 2007
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventors: Jo Frisson, David Modrie
  • Patent number: 7145945
    Abstract: The invention relates to an interference-free LMS-based asynchronous receiver for digital transmission and recording systems. The receiver, having an asynchronously placed LMS-based adaptive equalizer, has 2 control loops: a timing recovery loop (by means of, for instance a PLL (Phase locked loop) and an equalizer's adaptation loop. Interference between the two loops is avoided by deriving a condition the equalizer should fulfill to avoid the interference between the two loops, which implies “orthogonal control functionality” and by combining the condition with the equalizer's adaptation loop. The equalizer shall adapt so that the condition is always true.
    Type: Grant
    Filed: April 15, 2003
    Date of Patent: December 5, 2006
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: David Modrie, Willem Marie Coene
  • Publication number: 20060198467
    Abstract: A receiver is described for delivering a data sequence (ak) at a data rate 1/T from an analog signal (Sa), the receiver comprising: a) converting means (40) for generating a received sequence (rn) by sampling the analog signal (Sa) with a sample rate of 1/Ts, whereby the sample rate 1/Ts of the received sequence (rn) is controllable by a preset value (Pv); b) digital processing means (12) for delivering a processed sequence (yn) by processing the received sequence (rn); c) a first sample rate converter (13) for converting the processed sequence (yn) into an equivalent processed sequence (ye) at the data rate 1/T, whereby the data rate of the equivalent processed sequence (ye) is controllable by a control signal (Sc); d) an error generator (14) for delivering an error sequence (ek) from the equivalent processed sequence (ye); e) a control signal generating means (15) for generating the control signal (Sc) dependent on the error sequence (ek); f) a detector (16) for deriving the data sequence (ak) from the equi
    Type: Application
    Filed: April 30, 2003
    Publication date: September 7, 2006
    Inventors: David Modrie, Koen Vanhoof, Aalbert Stek
  • Publication number: 20050175128
    Abstract: The invention relates to an interference-free LMS-based asynchronous receiver for digital transmission and recording systems. The receiver, having an asynchronously placed LMS-based adaptive equalizer, has 2 control loops: a timing recovery loop (by means of, for instance a PLL (Phase locked loop) and an equalizer's adaptation loop. Interference between the two loops is avoided by deriving a condition the equalizer should fulfill to avoid the interference between the two loops, which implies “orthogonal control functionality” and by combining the condition with the equalizer's adaptation loop. The equalizer shall adapt so that the condition is always true.
    Type: Application
    Filed: April 15, 2003
    Publication date: August 11, 2005
    Inventors: David Modrie, Willem Coene
  • Publication number: 20050111540
    Abstract: The invention relates to an LMS-based asynchronous receiver for digital transmission and recording systems. The receiver comprises a digital adaptive equalizer (EQ) for receiving a received sequence rn and for delivering an equalized sequence yn. The equalizer (EQ) operates at the sampling rate 1/Ts, asynchronous to the data rate 1/T. An equalizer adaptation method using LMS techniques is described for adapting equalizer taps asynchronously to the data rate via a control loop. A first sampling rate converter (SRC1) performs timing recovery at the data rate 1/T after equalization on the equalized sequence yn. A second sampling rate converter (SRC2) is provided for converting a delayed version of the received sequence rn into an intermediate control sequence ik at the data rate 1/T.
    Type: Application
    Filed: October 30, 2002
    Publication date: May 26, 2005
    Inventors: David Modrie, Rob Otte