Abstract: A matrix by vector multiplication processing system (1) comprises a compression engine (2) for receiving and dynamically compressing a stream of elements of a matrix; in which the matrix elements are clustered, and in which the matrix elements are in numerical floating point format, and a memory (SDRAM, 3) for storing the compressed matrix. It also comprises a decompression engine (4) for dynamically decompressing elements retrieved from the memory (3), and a processor (10) for dynamically receiving decompressed elements from the decompression engine (3), and comprising a vector cache (13, 19), and multiplication logic (12, 21) for dynamically multiplying elements of the vector cache with the matrix elements. There is a cache (13) for vector elements to be multiplied by matrix elements to one side of a diagonal, and a separate cache or register (19) for vector elements to be multiplied by matrix elements to the other side of the diagonal.

Abstract: The device is to be used with a parallel architecture partial response maximum likelihood (PRML) reading apparatus comprising a variable-gain input amplifier, a low-pass analog filter, a transversal continuous-time analog filter and two distinct and parallel processing channels interposed between the transversal analog filter and an RLL-NRZ decoder. The two processing channels comprise respective analog-digital converters and respective Viterbi detectors and operate according to sampling sequences that alternate with one another. The device for processing the servo signals comprises a rectifier connected to the outputs of the analog-digital converters and an integrator.

Abstract: A device comprises a variable-gain input amplifier, a low-pass analog filter, a transversal continuous-time analog filter, and two distinct and parallel sampling channels interposed between the transversal analog filter and an RLL-NRZ decoder. The two sampling channels each comprise an analog-to-digital converter and a Viterbi detector arranged in series and operating according to sampling sequences that alternate with one another.

Abstract: The invention relates to a basic cell for comparing a first and a second digital signal, of the type having at least a first and a second input and a first and a second output and comprising at least one logic gate receiving digital signals at a first and a second signal input, and which comprises at least a first and a second controlled switch inserted in parallel with each other between the output terminal of the logic gate and the second output from the cell, the first switch being also connected between the first input and the first output of the cell and the second switch being also connected between the second input and the second output of the cell. The invention also relates to a digital comparator comprising a plurality of basic cells according to the invention.

Abstract: A programmable digital delay unit presenting a number of cascade-connected delay blocks, and a number of controlled bypass elements, one for each delay block. Each bypass element presents a bypass line and a multiplexer for selectively connecting the input or output of the respective delay block to the input of the next delay block. The delay blocks are formed by the cascade connection of flip-flops, and the number of flip-flops in each successive delay block, from the input of the delay unit, decreases in an arithmetic progression to the power of two, so that the selection signals for the respective multiplexers represent the bits of a digital word specifying the required delay.

Abstract: A zero-crossing circuit and method, in which the sign of inputs to a comparator is reversed after each zero crossing of the input signal. This means that delay introduced by the comparator does not affect the duty cycle of the output signal, so precision synchronization remains possible.

Abstract: A survival sequence register for a read channel employing a variable threshold peak qualification technique, has a first data shift register receiving a logic sum stream of two serial streams of coded digital data, corresponding to qualified peaks detected by a reading pick-up of positive and negative sign, respectively, and a pointer register. A control circuit generates an erase signal when an incoming pulse is recognized as corresponding to a detected peak of the same sign of the previously detected peak. The erase signal is input to logic gates which each drive a reset terminal of a flip-flop of the data shift register, with the exception of the first flip-flop of the register. The pointer register being reset when the control circuit receives a pulse corresponding to a peak of opposite polarity of the detected peak relative to the preceding pulse.

Abstract: A decoder for decoding a serial data stream employs an extracted base clock signal, synchronous with an input, coded, serial data stream, a first fractionary frequency clock signal for sampling a decoded output data stream and a second fractionary frequency clock signal for synthesizing a pre-decoded value, produced by a first combinative logic network, within a second combinative logic network to produce a decoded value that is sent to an output sampling flip-flop. In a decoder according to the present invention, a pipelined operation is implemented by momentarily storing the bits (part of the bits handled by the decoder) that are processed in the second combinative logic network and by anticipating of two full cycles of the synchronous base clock signal the processing, by said first combinative network, of the total n-number of bits handled by the decoder.

Abstract: A finite-state machine has combinatorial logic connected to a status memory which receives future state signals from the finite-state machine and sends current state signals to the finite-state machine. The combinatorial logic also receives and generates input and output signals which are external to the finite-state machine. The finite-state machine compares the future state signals to at least one reference level to set an error message to reset the finite-state machine for reliable computing and adjustment.

Abstract: A decoder of a coded serial stream of digital data in a stream of decoded NRZ data has re-timing (BB, AA) flip-flops and a 2.times.1 multiplexer (MUX OUT) selectably providing a single-bit NRZ output stream or a dual-bit (NRZ0 and NRZ1) output streams, by exploiting the predecoded values (ND0 and ND1) produced by two decoding combinative logic networks (RC1 and RC2) that compose the decoder.

Abstract: A transconductor stage for high-frequency filters operated on a low voltage supply, being of a type which comprises an input circuit portion having signal inputs, further comprises a pair of interconnected differential cells (2,3) being associated each with a corresponding signal input. Each cell incorporates at least one pair of bipolar transistors (Q1,Q2;Q3,Q4) having at least one corresponding terminal thereof (e.g. the emitter terminal) connected in common.

Abstract: A variable gain amplifier which includes a first voltage-to-current amplifier having a fixed gain; a second voltage-to-current amplifier having a variable gain, functioning in parallel to said first amplifier; a gain control and stabilization variable current generator; and a current-to-voltage converter. Current output signals produced by said first and second amplifiers and by said variable current generator are summed and the resulting current signal is converted to a voltage signal by said converter.

Abstract: The circuit structure comprises a series of storage units, a data bus, an address bus, a line for a reading/writing signal, a precharge logic suitable for precharging the address bus with a precharge address and a precharge sensor suitable for enabling the operation of address decoders of the storage units with a given delay with respect to the end of the precharge. The structure also comprises a flip-flop for controlling the address buses and the precharge logic as well as a delay circuit capable of producing a stop-writing signal with a delay calculated on the basis of the time necessary for the writing of a datum in a storage register of the storage units.

Abstract: A circuit device for neutralizing thermal drift in a transconductor differential stage using a first circuit portion which corresponds structurally to the transconductor differential stage and has a pair of MOS input transistors defining a transconductance value which is substantially proportional to that of the transconductor differential stage, a pair of bipolar output transistors coupled to the MOS input transistors in a cascode configuration, and a second circuit portion being supplied a current from an output of the first differential portion to thereby output a current to be passed to the transconductor differential stage. The value of the output current is inversely proportional to temperature-dependent parameters of the transconductance.

Abstract: A circuit particularly useful in AGC systems, produces an output current which is proportional to the difference between a signal voltage and a reference voltage which is practically independent of temperature. By being a function of a ratio among actual values of integrated resistances and of a ratio among substantially temperature-stable voltages. The effects of temperature dependent value of integrated resistances and of temperature-dependent electrical characteristics of integrated semiconductor devices are compensated in order to produce the desired temperature-independent output current which may usefully be utilized for implementing an automatic gain control.

Abstract: A circuit device for phasing an oscillator, which comprises a multivibrator having a transistor pair with the emitters coupled through a capacitor, comprises a normally open electronic switch controlled by a drive signal to close and inhibit the oscillator. This switch connects a voltage divider to the base of a transistor connected to one of the emitters to interrupt the loop positive feedback of the oscillator upon the voltage across the capacitor reaching a predetermined value.

Abstract: The tristate output gate structure particularly for CMOS integrated circuits, comprises an enable terminal receiving an enable signal and an input terminal receiving an input signal, which connects, through signal switching means, an output terminal to a positive power supply terminal or to a negative power supply terminal. The enable terminal can be electrically connected to the gate terminal of a first P-channel transistor through signal inverting means and to the gate terminal of a second N-channel transistor. The output terminal is electrically connected to the drain terminals of the first and second transistors. The first and second transistors electrically insulate the output terminal from the input terminal.

Abstract: A control circuit for an oscillator comprising a multivibrator with transistors having their emitters connected in common and being supplied corresponding currents on respective legs, comprises a circuit structure adapted to produce on output terminals, on the one side, a current which is proportional to a reference current according to a predetermined parameter, and on the other side, a second current in turn correlated to the reference current as a function of said parameter, thereby to modify the oscillator duty cycle for a given operating frequency.