Abstract: A hardware-configurable digital filter is adaptable for providing multiple filtering modes. In one embodiment, the digital filter includes a register-based array of logic circuitry, computational circuitry and mode selection circuitry. By reconfiguring data flow within the logic circuitry and the computational circuitry, the mode selection circuitry switches the digital filter between different ones of the multiple filtering modes. Each of the multiplication and addition logic circuits has outputs and inputs selectably coupled to the other of the multiplication and addition logic circuits along a Y direction, with the selectivity being responsive to the mode selection circuitry for arranging the registers as being functionally linear or functionally nonlinear.

Abstract: A hardware-configurable digital filter is adaptable for providing multiple filtering modes. In one embodiment, the digital filter includes a register-based array of logic circuitry, computational circuitry and mode selection circuitry. By reconfiguring data flow within the logic circuitry and the computational circuitry, the mode selection circuitry switches the digital filter between different ones of the multiple filtering modes. Each of the multiplication and addition logic circuits has outputs and inputs selectably coupled to the other of the multiplication and addition logic circuits along a Y direction, with the selectivity being responsive to the mode selection circuitry for arranging the registers as being functionally linear or functionally nonlinear.

Abstract: There are frames of three types, namely intraframes (I0), predicted frames (P3, P6) and interpolated or bidirectional frames (B1, B2). Each bidirectional frame is decoded twice in succession, a first time (1.sup.1) for obtaining a first field (1e) and displaying it as its decoding proceeds, while the second field is obtained in the course of the same decoding operation but is not used, and subsequently a second time (1.sub.2) for obtaining the second field (1o) and displaying it progressively. As the bidirectional frames are decoded and displayed in lines of blocks, the lines of blocks which are being decoded are located progressively in a memory, each time in place of a line of blocks whose contents have been displayed.

Abstract: Compression algorithms for digital video signals are based on processing of data blocks of frames which are of three types, i.e. intraframes, predicted frames, and interpolated or bidirectional frames (B). The memory space of the decoder is arranged in the form of five pages, four pages of which are used for each storing a field of the intraframe or predicted type. The fifth page is divided into sections each of which can store a line of blocks of a field of a bidirectional frame B. The bidirectional frames are decoded in successive stages of one line of blocks at a time, and the lines of blocks which are being decoded are stored progressively each time at the address in memory of a line of blocks the contents of which have already been displayed. The necessary memory space of the decoder is thereby reduced from six pages to five pages.