Abstract: The present disclosure is directed to a system and method for performing digital up-conversion of a signal to a desired RF carrier frequency. The system and method efficiently perform digital up-conversion of the signal, in one example, by controlling a sample clock that is used by a DAC to sample and convert the up-converted signal from the digital domain to the analog domain to have a frequency that is four or eight times the desired RF carrier frequency. By controlling the sample clock of the DAC to have a frequency that is four or eight times the desired RF carrier frequency, the system and method can be implemented using currently available IC process geometries such that the implementation consumes much less area and/or power than an analog up-converter configured to have equivalent up-conversion functionality.

Abstract: Disclosed are various embodiments providing processing circuitry that generates an output for each clock cycle of a clock signal using a logic block, the logic block being powered by a supply voltage. The processing circuitry detects whether the output has stabilized at a point in time before the end of a clock cycle of the clock signal, the point in time being based at least upon a delay line. In response to detecting whether the output has stabilized at a point in time, the processing circuitry dynamically adjusts at least one of the supply voltage or the frequency of the clock signal.

Abstract: The present disclosure is directed to a system and method for performing digital up-conversion of a signal to a desired RF carrier frequency. The system and method efficiently perform digital up-conversion of the signal, in one example, by controlling a sample clock that is used by a DAC to sample and convert the up-converted signal from the digital domain to the analog domain to have a frequency that is four or eight times the desired RF carrier frequency. By controlling the sample clock of the DAC to have a frequency that is four or eight times the desired RF carrier frequency, the system and method can be implemented using currently available IC process geometries such that the implementation consumes much less area and/or power than an analog up-converter configured to have equivalent up-conversion functionality.

Abstract: A scannable sequential element is provided. The scannable sequential element includes a master stage that includes a data path configured to receive a data input. The master stage also includes a pass gate located on the data path and configured to selectively pass the data input, in which the data path has only one pass gate. The master stage also includes a test path coupled to the data path and configured to receive a test input. The master stage also includes pass gates located on the test path and configured to selectively pass the test input.

Abstract: Disclosed are various embodiments providing processing circuitry that generates an output for each clock cycle of a clock signal using a logic block, the logic block being powered by a supply voltage. The processing circuitry detects whether the output has stabilized at a point in time before the end of a clock cycle of the clock signal, the point in time being based at least upon a delay line. In response to detecting whether the output has stabilized at the point in time, the processing circuitry dynamically adjusts at least one or the supply voltage or a frequency of the clock signal.

Abstract: An implicitly pulsed dual edge triggered pulsed latch. The implicitly pulsed latch includes an overlapping clock generator and a transparency circuit designed to cause a transparent latch circuit to become transparent on each edge of a clock signal. A logic value on the input node of the latch is transferred to the output node of the latch in response to each clock edge transition. An explicitly pulsed dual edge triggered pulsed latch including a pulse generator and a transparent latch circuit. The explicitly pulsed latch includes a symmetrical pulse generator designed to cause the latch circuit to pass a logic value from the input node of the latch to the output node of the latch in response to a pulse on the clock node.

Abstract: An approach is provided in embodiments of the present invention for building multiple-output static CMOS logic gate circuits that share transistors when computing multiple functions from a common set of inputs. In particular, an approach is provided which includes building multiple-output static NAND gates that compute the subfunctions of three or more inputs and building multiple-output static NOR gates that compute the subfunctions of two or more inputs. The approach also includes building multiple-output static XOR-XNOR gates that are capable of computing two-input XOR, three-input XOR, two-input XNOR, and three-input XNOR, and building multiple-output static Propagate-Generate (PG) compound gates. The approach further includes building carry propagate adders, priority encoders, binary-to-thermometers, decoders, etc. that are capable of using the multiple-output static gates embodied in the present invention.

Abstract: An implicitly pulsed dual edge triggered pulsed latch. The implicitly pulsed latch includes an overlapping clock generator and a transparency circuit designed to cause a transparent latch circuit to become transparent on each edge of a clock signal. A logic value on the input node of the latch is transferred to the output node of the latch in response to each clock edge transition. An explicitly pulsed dual edge triggered pulsed latch including a pulse generator and a transparent latch circuit. The explicitly pulsed latch includes a symmetrical pulse generator designed to cause the latch circuit to pass a logic value from the input node of the latch to the output node of the latch in response to a pulse on the clock node.