Abstract: A speed monitor circuit integrated in an integrated circuit (IC) determines the speed of the IC. The speed monitor circuit includes an oscillator that generates an oscillator signal. A speed determining circuit generates a first count based on transitions of the oscillator signal. A match signal corresponds to the speed of the oscillator based on the first count and a reference count.

Abstract: To facilitate measurement of the jitter tolerance of circuitry such as serializer/deserializer (SERDES) circuitry, test circuitry is provided that can add jitter to a data signal. The jitter added is preferably controllable and variable with respect to such parameters as jitter frequency (i.e., how rapid is the jitter) and/or amplitude (i.e., how large or great is the amount of the jitter).

Abstract: An integrated circuit comprises an oscillator that generates an oscillator signal. A first counter generates a first count based on transitions of the oscillator signal. A first circuit generates a match signal based on the first count and a reference count. A second counter generates a second count that is initialized at a starting count and adjusts the second count based on transitions of a reference clock signal. An output circuit outputs an oscillator speed based on the second count and the match signal. The oscillator speed is defined by a range that is independent of a frequency of the reference clock signal.

Abstract: A digitally controlled capacitor includes a first set of N capacitors, wherein the first set has a first capacitance value and each of the M capacitors has a second capacitance value, and at least one second set of N capacitors. The second set has the first capacitance value and each of the N capacitors has a third capacitance value that is greater than the second capacitance value. M and N are integers greater than one and M is not equal to N.

Abstract: To facilitate measurement of the jitter tolerance of circuitry such as serializer/deserializer (SERDES) circuitry, test circuitry is provided that can add jitter to a data signal. The jitter added is preferably controllable and variable with respect to such parameters as jitter frequency (i.e., how rapid is the jitter) and/or amplitude (i.e., how large or great is the amount of the jitter).

Abstract: A method of delaying an input signal comprises serially receiving the input signal at a plurality of rows of delay elements; applying a row selection signal to a row of delay elements to select the row from the plurality of rows; supplying a column selection signal to a tap buffer associated with a delay element in the selected row to select an output of the delay element; coupling outputs of tap buffers associated with delay elements in each row to form an output of each row; coupling outputs of each of the plurality of rows to provide an incrementally-delayed input signal from the selected row; outputting the incrementally-delayed input signal from the selected delay element in the selected row; and changing row selection from the selected row to a contiguous row of the plurality of rows in the absence of a change in the selection of the corresponding tap buffers.

Abstract: A circuit and related method of monitoring performance of an integrated circuit is provided comprising: using a variable oscillator that has an oscillation time period that varies within an expected range with variations in one or more of process, voltage or temperature to provide a signal that causes a count of a first counter to change at rate proportional to an oscillation frequency of the variable oscillator; using a clock source that has a frequency that substantially does not vary with variations in one or more of process, time or voltage to cause a count of a second counter to change at rate proportional to an oscillation frequency of the clock source; setting the second counter to start a count from a start; determining when the first counter has counted a reference count; and providing as a circuit speed, a value indicative of a count value produced by the second counter at about the moment when first counter finishes counting the count interval.

Abstract: A circuit generates a qualified data read strobe signal from a start burst signal and a bidirectional data strobe signal in a DDR memory control module. The circuit includes a delay module that receives the start burst signal and that generates a delayed start burst signal. An enable signal generator receives the delayed start burst signal and generates an enable signal. A first circuit generates the qualified data read strobe signal based on the enable signal and the bidirectional data strobe signal.

Abstract: A digitally controlled oscillator circuit is provided that comprises a ring oscillator including multiple inverters; multiple digitally controlled capacitors (DCCs), each coupled to apply a digitally controllable amount of capacitance to an output of a different one of the inverters; and control circuitry operable to change an amount of capacitance applied to each inverter during operation of the ring oscillator and to cause the multiple DCCs to apply substantially the same amounts of capacitance to each of the inverter throughout operation of the ring oscillator.

Abstract: To facilitate measurement of the jitter tolerance of circuitry such as serializer/deserializer (SERDES) circuitry, test circuitry is provided that can add jitter to a data signal. The jitter added is preferably controllable and variable with respect to such parameters as jitter frequency (i.e., how rapid is the jitter) and/or amplitude (i.e., how large or great is the amount of the jitter).

Abstract: To facilitate measurement of the jitter tolerance of circuitry such as serializer/deserializer (SERDES) circuitry, test circuitry is provided that can add jitter to a data signal. The jitter added is preferably controllable and variable with respect to such parameters as jitter frequency (i.e., how rapid is the jitter) and/or amplitude (i.e., how large or great is the amount of the jitter).

Abstract: A method of improving performance of a dual Vt integrated circuit is disclosed in which a first value is calculated for each transistor of the integrated circuit that has a first threshold voltage level. The first value is based at least in part on delay and leakage of the circuit calculated as if the corresponding transistor had a second threshold voltage level. One transistor is then selected based on the first values. The threshold voltage of the selected transistor is then set to the second threshold voltage level. The area of at least one transistor within the circuit is modified, and the circuit is then sized to a predetermined area. The process may then be repeated if the circuit performance fails to meet a defined constraint.

Abstract: High-gain synchronizer circuitry and methods are provided that reduce the meta-stable resolve time of a synchronizer circuit. The high-gain synchronizer is made up of high-gain latch circuits. The high-gain latch circuits are made up of a series of inverters that at least initially increase in size and that are connected in a closed loop. In accordance with the invention, the time that the high-gain synchronizer remains in the meta-stable state is minimized through the use of the high-gain latch circuits.

Abstract: To facilitate measurement of the jitter tolerance of circuitry such as serializer/deserializer (SERDES) circuitry, test circuitry is provided that can add jitter to a data signal. The jitter added is preferably controllable and variable with respect to such parameters as jitter frequency (i.e., how rapid is the jitter) and/or amplitude (i.e., how large or great is the amount of the jitter).

Abstract: To facilitate measurement of the jitter tolerance of circuitry such as serializer/deserializer (SERDES) circuitry, test circuitry is provided that can add jitter to a data signal. The jitter added is preferably controllable and variable with respect to such parameters as jitter frequency (i.e., how rapid is the jitter) and/or amplitude (i.e., how large or great is the amount of the jitter).

Abstract: A diagonal matrix delay includes a plurality of rows of first buffers in serial communication with an input signal. The diagonal matrix delay includes a plurality of second buffers. Each second buffer is responsive to an output of an associated first buffer and to a column selection signal. The diagonal matrix delay includes a plurality of control lines. Each control line supplies column selection signals to the corresponding second buffers associated with each of the plurality of rows. Corresponding second buffers controlled by a control line are offset between contiguous rows by at least one column to form a substantially diagonal arrangement of columns of second buffers relative to the plurality of rows of first buffers.

Abstract: A phase detector includes a first flip-flop responsive to a reference clock signal, a first inverter responsive to an output of the first flip-flop, a second flip-flop responsive to a feedback clock signal, a second inverter responsive to an output of the second flip-flop, a third inverter responsive to an output of the first inverter, a fourth inverter responsive to an output of the second inverter, a first conjunction circuit responsive to the output of the first inverter and to an output of the fourth inverter, and a second conjunction circuit responsive to the output of the second inverter and to an output of the third inverter. The first conjunction circuit outputs a first alignment signal when the feedback clock signal is earlier than the reference clock signal, and the second conjunction circuit outputs a second alignment signal when the feedback clock signal is later than the reference clock signal.

Abstract: A filter comprising of an internal memory for storing data and coefficients; an address generation unit, for generating memory addresses; a multiply and accumulate unit (i.e.—MAC unit), for performing multiply and accumulate functions. The filter can operate in a plurality of modes, such as multiple or single channel FIR filtering; multiple or single channel IIR filtering; multiple or single channel echo cancellation; multiple or single channel decimation and multiple or single channel extrapolation.

Abstract: An additional clock is delayed from a master clock by 90 degrees to provide needed additional clock edges during a cycle. The need for the additional clock edges arises from the desire to perform a read and a write in the same clock cycle. The precise delay is achieved through a clock programmable delay that can be updated as the frequency of the master clock may change. The amount of delay is conveniently detected by using two other programmable delays to achieve a 180 degree delay. The 180 degree delay is easily detected using a flip-flop. The programming signal that caused the total of 180 degrees of delay caused 90 degrees per programmable delay. The same programming signal is then coupled to the clock programmable delay to achieve the desired 90 degrees of delay for the additional clock.

Abstract: An additional clock is delayed from a master clock by 90 degrees to provide needed additional clock edges during a cycle. The need for the additional clock edges arises from the desire to perform a read and a write in the same clock cycle. The precise delay is achieved through a clock programmable delay that can be updated as the frequency of the master clock may change. The amount of delay is conveniently detected by using two other programmable delays to achieve a 180 degree delay. The 180 degree delay is easily detected using a flip-flop. The programming signal that caused the total of 180 degrees of delay caused 90 degrees per programmable delay. The same programming signal is then coupled to the clock programmable delay to achieve the desired 90 degrees of delay for the additional clock.