Abstract: A method for retaining service configuration during test connection to a pseudowire service is disclosed. The method for retaining service configuration during test connection includes the steps of configuring a test service access point; providing a first instruction at a first network element to lock the pseudowire connection; providing a second instruction at a second network element to lock the pseudowire connection; receiving an instruction at said the network element to associate a test service provided at a network management element to said first Service Distribution Point; and providing a loopback instruction to the pseudowire connection. The method for retaining service configuration during test connection to a pseudowire service provides advantages over systems known in the art by eliminating the need for reconfiguring the connection to customer equipment at the point of test and afterwards.

Abstract: Various exemplary embodiments relate to a method performed by a backbone network for performing switchover of plurality of pseudo-wires (PWs) connecting a customer edge device to a primary backbone edge bridge (BEB), the method including: designating one of the plurality of PWs as a control PW; associating the remaining PWs with the control PW; associating a virtual backbone MAC (B-MAC) address with the control PW; and advertising, by the primary BEB, the virtual B-MAC address to the backbone network.

Abstract: Apparatus and methods for autonomously identifying and mitigating soft-errors affecting integrated circuit memory storage devices are provided. A soft-error mitigation process is invoked upon finding that an integrated circuit memory device is affected by a parity error. In a staged approach, unused memory regions of the integrated circuit memory device are reinitialized; if a redundant deployment prevails, the subsystem corresponding to the affected integrated circuit memory device is reset; memory regions having copies of contents thereof stored at remote locations are rewritten with obtained copies of the contents; and memory regions storing contents which are generated at run-time are reinitialized. Directed parity error scans are employed at each stage. If the parity error persists, one of the apparatus, and the subsystem corresponding to the affected silicon memory device is reset during a maintenance window.

Abstract: Apparatus and methods for autonomously identifying and mitigating soft-errors affecting integrated circuit memory storage devices are provided. A soft-error mitigation process is invoked upon finding that an integrated circuit memory device is affected by a parity error. In a staged approach, unused memory regions of the integrated circuit memory device are reinitialized; if a redundant deployment prevails, the subsystem corresponding to the affected integrated circuit memory device is reset; memory regions having copies of contents thereof stored at remote locations are rewritten with obtained copies of the contents; and memory regions storing contents which are generated at run-time are reinitialized. Directed parity error scans are employed at each stage. If the parity error persists, one of the apparatus, and the subsystem corresponding to the affected silicon memory device is reset during a maintenance window.