Abstract: A circuit arrangement with standby mode minimizing power and/or current consumption having a mains AC power supply terminals and an active circuit capable of converting said mains AC power to lower voltage DC levels for operating in an active mode or in a standby mode as required by an appliance such that the selection of the current sensing resistor value for said current sensing resistor limits the maximum peak current through the FET so that the current sensing resistor arrangement is capable of providing significant increases in a steeper rise time of the current at around mains AC power supply zero crossing, so that current is pulled high while the mains AC power supply voltage is low.

Abstract: An electrical relay contact arrangement for switching an electrical relay ‘on’ or ‘off’ at zero crossings of an AC mains supply, wherein the arrangement rather than immediately sending a control signal from a microprocessor to the input of the electrical relay to close or open the mechanical electrode contacts when switching is required, relies upon a time interval made up two delays, firstly when the microprocessor first recognizes switching is required there is a waiting period until the next zero crossing, and then a further delay which is the time difference between the lag times of the mechanical contact electrodes physically opening or closing and that of the next zero crossing.

Abstract: A circuit arrangement with standby mode minimising power and/or current consumption having a mains AC power supply terminals and an active circuit capable of converting said mains AC power to lower voltage DC levels for operating in an active mode or in a standby mode as required by an appliance such that the selection of the current sensing resistor value for said current sensing resistor limits the maximum peak current through the FET so that the current sensing resistor arrangement is capable of providing significant increases in a steeper rise time of the current at around mains AC power supply zero crossing, so that current is pulled high while the mains AC power supply voltage is low.

Abstract: A bus buffer can include a data buffer and a clock signal buffer. The data buffer for can include two symmetrical buffer circuits with an output signal that can follow the input voltage to provide bi-directional buffer action for a data path of the bus buffer. The clock buffer can operate in a forward or reverse direction, where the signal direction for the clock signal path in the bus buffer can be controlled with a direction input. The bus buffer can also include an enable circuit for enabling the data path and the clock signal path.

Abstract: A bus buffer can include a data buffer and a clock signal buffer. The data buffer for can include two symmetrical buffer circuits with an output signal that can follow the input voltage to provide bi-directional buffer action for a data path of the bus buffer. The clock buffer can operate in a forward or reverse direction, where the signal direction for the clock signal path in the bus buffer can be controlled with a direction input. The bus buffer can also include an enable circuit for enabling the data path and the clock signal path.

Abstract: A bi-directional bus buffer for applications using the I2C and SMBus, or other bus systems operating on similar principles, able to extend the bus load limit by buffering both the SCL and SDA (clock and data) lines, allowing capacitive loads of up to the limit of 400 pF on both sides of the buffer. With the use of an enable function, sections of the bus can be isolated, and then, thorough the use of a number of these buffers, different parts of the system are able to be isolated, and brought on-line successively or in a controlled manner, permitting a controlled start-up, and operation at maximum performance speeds while still having a diverse range of components, operating speeds and loads.

Abstract: A bi-directional bus buffer for applications using the I2C and SMBus, or other bus systems operating on similar principles, able to extend the bus load limit by buffering both the SCL and SDA (clock and data) lines, allowing capacitive loads of up to the limit of 400 pF on both sides of the buffer. With the use of an enable function, sections of the bus can be isolated, and then, thorough the use of a number of these buffers, different parts of the system are able to be isolated, and brought on-line successively or in a controlled manner, permitting a controlled start-up, and operation at maximum performance speeds while still having a diverse range of components, operating speeds and loads.