Patents by Inventor David N. Dixon

David N. Dixon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Technique for modeling parasitics from layout during circuit design and for parasitic aware circuit design using modes of varying accuracy
    Patent number: 8612921
    Abstract: A user is presented with a simulation environment within which the user is provided a choice to select between parasitic simulation modes of varying accuracy, the modes including a mode without parasitics and a plurality of modes including parasitics with a varying degree of accuracy. A selection from among the modes is received from the user and simulation test are performed at the selected degree of accuracy.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: December 17, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Prakash Gopalakrishnan, Rongchang Yan, Akshat H. Shah, David N. Dixon, Keith Dennison
  • Technique for modeling parasitics from layout during circuit design and for parasitic aware circuit design using modes of varying accuracy
    Patent number: 8584072
    Abstract: A user is presented with a simulation environment within which the user is provided a choice to select between parasitic simulation modes of varying accuracy, the modes including a mode without parasitics and a plurality of modes including parasitics with a varying degree of accuracy. A selection from among the modes is received from the user and simulation test are performed at the selected degree of accuracy.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: November 12, 2013
    Assignee: Cadence Design Systems, Inc.
    Inventors: Prakash Gopalakrishnan, Rongchang Yan, Akshat H. Shah, David N. Dixon, Keith Dennison
  • Technique for modeling parasitics from layout during circuit design and for parasitic aware circuit design using modes of varying accuracy
    Patent number: 8261228
    Abstract: Techniques are presented for accounting for parasitics in the automated design of integrated circuits. In one set of techniques, model values for parasitic models are received on a schematic environment from a user, the parasitic models are evaluated from the schematic using the received model values, the parasitic models are transferred to a layout environment, and the transferred parasitic models are evaluated on the layout environment. In other techniques, model values are received for parasitic models from a user, the parasitic models are evaluated on the layout environment, and the process then backannotates the parasitic models evaluated on the layout environment and corresponding parameter values to a schematic environment.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: September 4, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Prakash Gopalakrishnan, Rongchang Yan, Akshat H. Shah, David N. Dixon, Keith Dennison