Abstract: A method and apparatus are provided for accessing data. The method includes defining a first portion of a memory for receiving data and providing a memory request to transfer data from a source to the first portion of the memory defined to receive the data. The method further includes transferring a portion of data from the source to the first portion of the memory, wherein the size of the portion of the data substantially corresponds to the size of the first portion of the memory.

Abstract: An apparatus is provided that includes a data controller, a subscriber line audio-processing circuit, and a controller. The data controller includes an input terminal and an output terminal capable of providing packet data. The subscriber line audio-processing circuit is capable of providing signals in a voice band. The controller is capable of transmitting at least one of signals in the voice band from the subscriber line audio-processing circuit and the packet data from the output terminal of the data controller.

Abstract: A method and apparatus are provided for encrypting a stream of data transmitted within a frame. The method includes determining a first initialization state in a first preselected interval, and determining the first initialization state in a second preselected interval, wherein the second preselected interval is less than the first preselected interval. The method includes generating a key stream in response to determining the first initialization state in the second preselected interval, and encrypting at least one bit of the stream of data with at least one bit of the key stream.

Abstract: A method and apparatus are provided, where the method includes defining a first portion of a memory for receiving data, providing a memory request to transfer data from a source to the first portion of the memory defined to receive the data, and transferring a portion of data from the source to the first portion of the memory according to a priority scheme that determines the sequence of the data transfer, wherein the size of the portion of the data substantially corresponds to the size of the first portion of the memory. The method also includes associating a frame with at least one corresponding memory location containing data in the first portion of the memory, transmitting at least a portion of data from the first portion of the memory within the frame, and receiving an acknowledgement in response to transmitting the data within the frame.

Abstract: A method and apparatus are provided for accessing data. The method includes defining a first portion of a memory for receiving data and providing a memory request to transfer data from a source to the first portion of the memory defined to receive the data. The method further includes transferring a portion of data from the source to the first portion of the memory, wherein the size of the portion of the data substantially corresponds to the size of the first portion of the memory.

Abstract: A method and apparatus are provided, where the method and apparatus include associating a frame with at least one corresponding memory location that contains data, transmitting the data within the frame to a peer station, receiving an acknowledgement in response to transmitting the data within the frame from the peer station, analyzing the acknowledgement to determine if the data within the frame transmits successfully, and updating the corresponding memory location with new data in response to determining if the data transmits successfully.

Abstract: A method and apparatus are provided for accessing data. The method includes defining a first portion of a memory for receiving data and providing a memory request to transfer data from a source to the first portion of the memory defined to receive the data. The method further includes transferring a portion of data from the source to the first portion of the memory, wherein the size of the portion of the data substantially corresponds to the size of the first portion of the memory.

Abstract: A method and apparatus are provided, where method includes defining a first portion of a memory for receiving data and providing a memory request to transfer data from a source to the first portion of the memory defined to receive the data. The method further includes transferring a portion of data from the source to the first portion of the memory according to a priority scheme that determines the sequence of the data transfer, wherein the size of the portion of the data substantially corresponds to the size of the first portion of the memory.

Abstract: A resistor-capacitor oscillator circuit (10) is provided and includes a voltage comparator circuit (12). A capacitor (20) is connected to an input terminal (14) of the voltage comparator circuit (12). A resistor divider network (30) is coupled to an input terminal (16) of the voltage comparator circuit (12) for generating a reference voltage. A delay circuit (50, 52) is coupled to an output terminal (42) of the voltage comparator circuit (12). A discharge device (54) is coupled to the delay circuit (50, 52) and to the capacitor (20) for discharging the capacitor (20). A switching device (40) is coupled to the output (42) of the voltage comparator circuit (12) and to the resistor divider network (30) for controlling the application of the reference voltage to voltage comparator circuit (12).

Abstract: A memory cell (10) for storing data having a data line (12) and a bit enable line (16) for receiving control signals is provided. First and second signal lines (24, 26) receive control signals. A first transistor (14) is interconnected to the data line (12) and to the bit enable line (16). A second transistor (20) is connected to the first transistor (14) and to the first control line (24). A third transistor (22) is connected to the first transistor (14) and to the second control line (26). A first inverter (30) is interconnected to the second transistor (20) to form a first node (34) and to the third transistor (22) to form a second node (36). A second inverter (32) is interconnected between the first node (34) and the second node (36).

Abstract: An option select circuit for a dialer includes an internal address generator (20) for generating an address pattern, which, in a set up mode, is output from a multiplexer (14) to I/O pins (10). The pins (10) are selectively hardwired through an interface circuit (24) back to address input pins (50) and (52) for input to a decorder (28). The decoder (28) decodes the selected address for input to a PLA (30). This allows selection of various functions in a function generator (12) for operation in the normal dialer mode. The interface circuit (24) comprises hardwire connections (54) and (56).