Patents by Inventor David N. Lombard
David N. Lombard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230101997Abstract: Disclosed herein are embodiments of systems and methods for stable and elevated idle-mode temperature for assembled semiconductor devices. In an embodiment, a processor includes a communication interface configured to receive, from a first hardware component, instructions assigned to the processor for execution. The processor also includes temperature-measurement circuitry configured to monitor an on-chip temperature of the processor. The processor also includes control logic configured to: determine whether the processor is active or idle; determine whether the on-chip temperature of the processor exceeds a first threshold; based on determining that the processor is idle and that the on-chip temperature of the processor exceeds the first threshold, disable one or more idle-mode power-saving features of the processor; and selectively adjust one or more operating parameters of the processor to keep the on-chip temperature of the processor between the first threshold and a second (higher) threshold.Type: ApplicationFiled: September 30, 2021Publication date: March 30, 2023Inventors: Nikos Kaburlasos, Rodrigo De Oliveira Vivi, Phani Kumar Kandula, Marc Beuchat, Mark J. Luckeroth, Eric J.M. Moret, David N. Lombard, John Kelbert, Brad Bittel
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Patent number: 10817454Abstract: An apparatus includes physical layer circuitry with lanes to couple the apparatus to endpoint devices. a first input/output (I/O) controller to couple a first processor to the physical layer circuitry, and a second I/O controller to couple a second processor to the physical layer circuitry. The first and second I/O controllers are compatible with a Peripheral Component Interconnect Express (PCIe)-based protocol. The apparatus also includes a flexible input/output adapter (FIA) coupling the first and second I/O controllers to the lanes. The FIA selectively assigns access to each lane of the lanes by either the first or second I/O controller. The apparatus also includes a power management controller (PMC) communicably coupled to the FIA. The PMC causes the FIA to dynamically assign access to at least one of the lanes by the first or second I/O controller without a reboot cycle.Type: GrantFiled: April 26, 2019Date of Patent: October 27, 2020Assignee: Intel CorporationInventors: Chih-Cheh Chen, Janusz P. Jurski, Amit Kumar Srivastava, Malay Trivedi, James Mitchell, Piotr Michael Kwidzinski, David N. Lombard
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Patent number: 10521002Abstract: Apparatus, systems, and methods provide dynamic spatial power steering among a plurality of power domains in the computer system on a per phase basis of a particular application. Dynamic spatial power steering may include, for example, determining a plurality of phases corresponding to an application comprising tasks for execution on a processing node. determining a spatial power distribution between a plurality of power domains on the processing node based on a performance metric for each phase, monitoring the application to detect a current phase, and applying the spatial power distribution correspond to the current phase to the plurality of power domains.Type: GrantFiled: October 19, 2017Date of Patent: December 31, 2019Assignee: INTEL CORPORATIONInventors: Jonathan M. Eastep, Rohit Banerjee, Richard J. Greco, Ilya Sharapov, David N. Lombard, Hari K. Nagpal
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Patent number: 10466754Abstract: Systems and methods may provide a set of networked computational resources such as nodes that may be arranged in a hierarchy. A hierarchy of performance balancers receives performance samples from the computational resources beneath them and uses the performance samples to conduct a statistical analysis of variations in their performance. In one embodiment, the performance balancers steer power from faster resources to slower resources in order to enhance their performance, including in parallel processing.Type: GrantFiled: December 26, 2014Date of Patent: November 5, 2019Assignee: Intel CorporationInventors: Jonathan M. Eastep, Ilya Sharapov, Richard J. Greco, Steve S. Sylvester, David N. Lombard
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Publication number: 20190251055Abstract: An apparatus includes physical layer circuitry with lanes to couple the apparatus to endpoint devices. a first input/output (I/O) controller to couple a first processor to the physical layer circuitry, and a second I/O controller to couple a second processor to the physical layer circuitry. The first and second I/O controllers are compatible with a Peripheral Component Interconnect Express (PCIe)-based protocol. The apparatus also includes a flexible input/output adapter (FIA) coupling the first and second I/O controllers to the lanes. The FIA selectively assigns access to each lane of the lanes by either the first or second I/O controller. The apparatus also includes a power management controller (PMC) communicably coupled to the FIA. The PMC causes the FIA to dynamically assign access to at least one of the lanes by the first or second I/O controller without a reboot cycle.Type: ApplicationFiled: April 26, 2019Publication date: August 15, 2019Applicant: Intel CorporationInventors: Chih-Cheh Chen, Janusz P. Jurski, Amit Kumar Srivastava, Malay Trivedi, James Mitchell, Piotr Michael Kwidzinski, David N. Lombard
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Publication number: 20180059768Abstract: Apparatus, systems, and methods provide dynamic spatial power steering among a plurality of power domains in the computer system on a per phase basis of a particular application. Dynamic spatial power steering may include, for example, determining a plurality of phases corresponding to an application comprising tasks for execution on a processing node. determining a spatial power distribution between a plurality of power domains on the processing node based on a performance metric for each phase, monitoring the application to detect a current phase, and applying the spatial power distribution correspond to the current phase to the plurality of power domains.Type: ApplicationFiled: October 19, 2017Publication date: March 1, 2018Applicant: INTEL CORPORATIONInventors: Jonathan M. Eastep, Rohit Banerjee, Richard J. Greco, Ilya Sharapov, David N. Lombard, Hari K. Nagpal
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Patent number: 9811143Abstract: Apparatus, systems, and methods provide dynamic spatial power steering among a plurality of power domains in the computer system on a per phase basis of a particular application. Dynamic spatial power steering may include, for example, determining a plurality of phases corresponding to an application comprising tasks for execution on a processing node. determining a spatial power distribution between a plurality of power domains on the processing node based on a performance metric for each phase, monitoring the application to detect a current phase, and applying the spatial power distribution correspond to the current phase to the plurality of power domains.Type: GrantFiled: December 23, 2014Date of Patent: November 7, 2017Assignee: INTEL CORPORATIONInventors: Jonathan M. Eastep, Rohit Banerjee, Richard J. Greco, Ilya Sharapov, David N. Lombard, Hari K. Nagpal
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Patent number: 9477533Abstract: Systems and methods may provide a set of cores capable of parallel execution of threads. Each of the cores may run code that is provided with a progress meter that calculates the amount of work remaining to be performed on threads as they run on their respective cores. The data may be collected continuously, and may be used to alter the frequency, speed or other operating characteristic of the cores as well as groups of cores. The progress meters may be annotated into existing code.Type: GrantFiled: December 26, 2014Date of Patent: October 25, 2016Assignee: Intel CorporationInventors: Jonathan M. Eastep, Ilya Sharapov, Rob F. Van Der Wijngaart, Richard J. Greco, Steve S. Sylvester, David N. Lombard
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Publication number: 20160188380Abstract: Systems and methods may provide a set of cores capable of parallel execution of threads. Each of the cores may run code that is provided with a progress meter that calculates the amount of work remaining to be performed on threads as they run on their respective cores. The data may be collected continuously, and may be used to alter the frequency, speed or other operating characteristic of the cores as well as groups of cores. The progress meters may be annotated into existing code.Type: ApplicationFiled: December 26, 2014Publication date: June 30, 2016Inventors: Jonathan M. Eastep, Ilya Sharapov, Rob F. Van Der Wijngaart, Richard J. Greco, Steve S. Sylvester, David N. Lombard
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Publication number: 20160187944Abstract: Systems and methods may provide a set of networked computational resources such as nodes that may be arranged in a hierarchy. A hierarchy of performance balancers receives performance samples from the computational resources beneath them and uses the performance samples to conduct a statistical analysis of variations in their performance. In one embodiment, the performance balancers steer power from faster resources to slower resources in order to enhance their performance, including in parallel processing.Type: ApplicationFiled: December 26, 2014Publication date: June 30, 2016Inventors: Jonathan M. Eastep, Ilya Sharapov, Richard J. Greco, Steve S. Sylvester, David N. Lombard
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Publication number: 20160179173Abstract: Apparatus, systems, and methods provide dynamic spatial power steering among a plurality of power domains in the computer system on a per phase basis of a particular application. Dynamic spatial power steering may include, for example, determining a plurality of phases corresponding to an application comprising tasks for execution on a processing node. determining a spatial power distribution between a plurality of power domains on the processing node based on a performance metric for each phase, monitoring the application to detect a current phase, and applying the spatial power distribution correspond to the current phase to the plurality of power domains.Type: ApplicationFiled: December 23, 2014Publication date: June 23, 2016Applicant: Intel CorporationInventors: JONATHAN M. EASTEP, ROHIT BANERJEE, RICHARD J. GRECO, ILYA SHARAPOV, DAVID N. LOMBARD, HARI K. NAGPAL
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Patent number: 8386594Abstract: An embodiment may include network controller circuitry to be included in a first host computer that includes a host processor to execute an operating system environment. The circuitry may initiate, at least in part, one or more checkpoints of, at least in part, one or more states associated with, at least in part, the operating system environment and network traffic between the first host computer and a second host computer. The circuitry also may coordinate, at least in part, respective execution, at least in part, of the one or more checkpoints with respective execution of one or more other respective checkpoints of the second host computer. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.Type: GrantFiled: February 11, 2010Date of Patent: February 26, 2013Assignee: Intel CorporationInventors: Keith D. Underwood, David N. Lombard, Jan Uerpmann, Steffen Kosinski
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Publication number: 20110196950Abstract: An embodiment may include network controller circuitry to be included in a first host computer that includes a host processor to execute an operating system environment. The circuitry may initiate, at least in part, one or more checkpoints of, at least in part, one or more states associated with, at least in part, the operating system environment and network traffic between the first host computer and a second host computer. The circuitry also may coordinate, at least in part, respective execution, at least in part, of the one or more checkpoints with respective execution of one or more other respective checkpoints of the second host computer. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.Type: ApplicationFiled: February 11, 2010Publication date: August 11, 2011Inventors: Keith D. Underwood, David N. Lombard, Jan Uerpmann, Steffen Kosinski