Patents by Inventor David N. Okada
David N. Okada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10707327Abstract: A semiconductor device includes a semiconductor substrate including a doped region. A metal layer is formed on the doped region. An insulating layer covers the metal layer. The metal layer can serve as a buried metal layer which reduces electrical resistance between electrical charge in the doped region and adjacent contacts. The contacts can extend through the insulating layer between the buried metal layer and overlying metal stripes.Type: GrantFiled: December 28, 2015Date of Patent: July 7, 2020Assignee: Great Wall Semiconductor CorporationInventors: Patrick M. Shea, David N. Okada, Samuel J. Anderson
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Publication number: 20190165093Abstract: A semiconductor device has a substrate and a lightly doped drain (LDD) region formed in the substrate. A superjunction is formed in the LDD region.Type: ApplicationFiled: January 31, 2019Publication date: May 30, 2019Inventors: Patrick M. SHEA, Samuel J. ANDERSON, David N. OKADA
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Patent number: 10199459Abstract: A semiconductor device has a substrate and a lightly doped drain (LDD) region formed in the substrate. A superjunction is formed in the LDD region.Type: GrantFiled: March 25, 2016Date of Patent: February 5, 2019Assignee: Great Wall Semiconductor CorporationInventors: Patrick M. Shea, Samuel J. Anderson, David N. Okada
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Patent number: 9640638Abstract: A semiconductor device has a substrate and gate structure over the substrate. A source region is formed in the substrate adjacent to the gate structure. A drain region in the substrate adjacent to the gate structure opposite the source region. An interconnect structure is formed over the substrate by forming a conductive plane electrically connected to the source region, and forming a conductive layer within openings of the conductive plane and electrically connected to the drain region. The interconnect structure can be formed as stacked conductive layers laid out in alternating strips. The conductive plane extends under a gate terminal of the semiconductor device. An insulating layer is formed over the substrate and a field plate is formed in the insulating layer. The field plate is electrically connected the source terminal. A stress relief layer is formed over a surface of the substrate opposite the gate structure.Type: GrantFiled: January 22, 2013Date of Patent: May 2, 2017Assignee: GREAT WALL SEMICONDUCTOR CORPORATIONInventors: Samuel J. Anderson, David N. Okada, Patrick M. Shea
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Publication number: 20160308015Abstract: A semiconductor device comprises a semiconductor substrate including a doped region. A metal layer is formed on the doped region. An insulating layer covers the metal layer.Type: ApplicationFiled: December 28, 2015Publication date: October 20, 2016Applicant: Great Wall Semiconductor CorporationInventors: Patrick M. Shea, David N. Okada, Samuel J. Anderson
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Publication number: 20160211365Abstract: A semiconductor device has a substrate and a lightly doped drain (LDD) region formed in the substrate. A superjunction is formed in the LDD region.Type: ApplicationFiled: March 25, 2016Publication date: July 21, 2016Applicant: Great Wall Semiconductor CorporationInventors: Patrick M. Shea, Samuel J. Anderson, David N. Okada
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Patent number: 9299774Abstract: A semiconductor device has a substrate and a gate formed over the substrate. An LDD region is formed in the substrate adjacent to the gate. A superjunction is formed in the LDD region while a portion of the LDD region remains between the superjunction and gate. A mask is formed over the substrate. A first region is doped with a first type of dopant using the mask. A stripe is doped with a second type of dopant using a portion of the mask. A drain contact region is formed in the substrate. The first region extends to the drain contact region. The first region and stripe are formed using chain implants. A source field plate and drain field plate are formed over the substrate. A trench is formed in the substrate. A source contact region is formed in the trench.Type: GrantFiled: July 16, 2014Date of Patent: March 29, 2016Assignee: Great Wall Semiconductor CorporationInventors: Patrick M. Shea, Samuel J. Anderson, David N. Okada
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Patent number: 9099519Abstract: A semiconductor device has a substrate and first and second gate structures formed over a first surface of the substrate. A drain region is formed in the substrate as a second surface of the substrate. An epitaxial region is formed in the substrate over the drain region. A sidewall spacer is formed over the first and second gate structures. A lateral LDD region is formed between the first and second gate structures. A trench is formed through the lateral LDD region and partially through the substrate self-aligned to the sidewall spacer. A vertical drift region is formed along a sidewall of the trench. An insulating material is deposited in the trench. A first source region is formed adjacent to the first gate structure opposite the lateral LDD region. A second source region is formed adjacent to the second gate structure opposite the lateral LDD region.Type: GrantFiled: May 23, 2012Date of Patent: August 4, 2015Assignee: Great Wall Semiconductor CorporationInventors: Zheng John Shen, Patrick M. Shea, David N. Okada
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Patent number: 9018706Abstract: A cell phone has a plurality of interconnected electronic components for performing the electrical functions of the phone. A DC/DC converter provides an operating voltage which is applied to power supply terminals of the plurality of interconnected electronic components. The DC/DC converter uses a monolithic semiconductor device containing a power metal oxide semiconductor field effect transistor (MOSFET) and Schottky diode. The semiconductor device has the lateral diffused MOSFET formed on a surface of the semiconductor device. The MOSFET is formed with a plurality conduction fingers. The Schottky diode is also formed on the surface of the semiconductor device and integrated between the plurality of conduction fingers of the MOSFET. The drain of the MOSFET is connected to the anode of the diode on the surface of the monolithic semiconductor device.Type: GrantFiled: April 24, 2014Date of Patent: April 28, 2015Assignee: Great Wall Semiconductor CorporationInventors: Samuel J. Anderson, David N. Okada
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Patent number: 9006099Abstract: A semiconductor device has a substrate with a source region and a drain region formed on the substrate. A silicide layer is disposed over the source region and drain region. A first interconnect layer is formed over the silicide layer and includes a first runner connected to the source region and second runner connected to the drain region. A second interconnect layer is formed over the first interconnect layer and includes a third runner connected to the first runner and a fourth runner connected to the second runner. An under bump metallization (UBM) is formed over and electrically connected to the second interconnect layer. A mask is disposed over the substrate with an opening in the mask aligned over the UBM. A conductive bump material is deposited within the opening in the mask. The mask is removed and the conductive bump material is reflowed to form a bump.Type: GrantFiled: June 8, 2011Date of Patent: April 14, 2015Assignee: Great Wall Semiconductor CorporationInventors: Samuel J. Anderson, David N. Okada
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Patent number: 8962425Abstract: A semiconductor device has a substrate and trench formed partially through the substrate. A drain region is formed in the substrate as a second surface of the substrate. An epitaxial region is formed in the substrate over the drain region. A vertical drift region is formed along a sidewall of the trench. An insulating material is deposited within the trench. A channel region is formed along the sidewall of the trench above the insulating material. The channel region is separated from the insulating material. A gate structure is formed within the trench adjacent to the channel region. The gate structure includes an insulating layer formed along the sidewall of the trench adjacent to the channel region and polysilicon layer formed within the trench over the insulating layer. A source region is formed in a first surface of the substrate contacting the channel region.Type: GrantFiled: May 23, 2012Date of Patent: February 24, 2015Assignee: Great Wall Semiconductor CorporationInventors: Zheng John Shen, Patrick M. Shea, David N. Okada
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Publication number: 20150021686Abstract: A semiconductor device has a substrate and a gate formed over the substrate. An LDD region is formed in the substrate adjacent to the gate. A superjunction is formed in the LDD region while a portion of the LDD region remains between the superjunction and gate. A mask is formed over the substrate. A first region is doped with a first type of dopant using the mask. A stripe is doped with a second type of dopant using a portion of the mask. A drain contact region is formed in the substrate. The first region extends to the drain contact region. The first region and stripe are formed using chain implants. A source field plate and drain field plate are formed over the substrate. A trench is formed in the substrate. A source contact region is formed in the trench.Type: ApplicationFiled: July 16, 2014Publication date: January 22, 2015Inventors: Patrick M. Shea, Samuel J. Anderson, David N. Okada
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Patent number: 8921186Abstract: A semiconductor device has a buried oxide layer formed over a substrate. An active silicon layer is formed over the buried oxide layer. A drain region is formed in the active silicon layer. An LDD drift region is formed in the active silicon layer adjacent to the drain region. The drift region has a graded doping distribution. A co-implant region is formed in the active silicon. A source region is formed in the co-implant region. A shallow trench insulator is formed along a top surface of the LDD drift region. The shallow trench isolator has a length less than the LDD drift region. The shallow trench insulator terminates under the polysilicon gate and within the LDD drift region. A polysilicon gate is formed above the active silicon layer between the source region and LDD drift region and at least partially overlapping the shallow trench insulator.Type: GrantFiled: May 15, 2009Date of Patent: December 30, 2014Assignee: Great Wall Semiconductor CorporationInventors: Patrick M. Shea, Samuel J. Anderson, David N. Okada
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Patent number: 8895430Abstract: A semiconductor device has a semiconductor wafer with a plurality of semiconductor die including a plurality of contact pads. An insulating layer is formed over the semiconductor wafer and contact pads. An under bump metallization (UBM) is formed over and electrically connected to the plurality of contact pads. A mask is disposed over the semiconductor wafer with a plurality of openings aligned over the plurality of contact pads. A conductive bump material is deposited within the plurality of openings in the mask and onto the UBM. The mask is removed. The conductive bump material is reflowed to form a plurality of bumps with a height less than a width. The plurality of semiconductor die is singulated. A singulated semiconductor die is mounted to a substrate with bumps oriented toward the substrate. Encapsulant is deposited over the substrate and around the singulated semiconductor die.Type: GrantFiled: March 29, 2012Date of Patent: November 25, 2014Assignee: Great Wall Semiconductor CorporationInventors: Samuel J. Anderson, Gary Dashney, David N. Okada
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Publication number: 20140231901Abstract: A cell phone has a plurality of interconnected electronic components for performing the electrical functions of the phone. A DC/DC converter provides an operating voltage which is applied to power supply terminals of the plurality of interconnected electronic components. The DC/DC converter uses a monolithic semiconductor device containing a power metal oxide semiconductor field effect transistor (MOSFET) and Schottky diode. The semiconductor device has the lateral diffused MOSFET formed on a surface of the semiconductor device. The MOSFET is formed with a plurality conduction fingers. The Schottky diode is also formed on the surface of the semiconductor device and integrated between the plurality of conduction fingers of the MOSFET. The drain of the MOSFET is connected to the anode of the diode on the surface of the monolithic semiconductor device.Type: ApplicationFiled: April 24, 2014Publication date: August 21, 2014Applicant: Great Wall Semiconductor CorporationInventors: Samuel J. Anderson, David N. Okada
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Publication number: 20130313640Abstract: A semiconductor device has a substrate and first and second gate structures formed over a first surface of the substrate. A drain region is formed in the substrate as a second surface of the substrate. An epitaxial region is formed in the substrate over the drain region. A sidewall spacer is formed over the first and second gate structures. A lateral LDD region is formed between the first and second gate structures. A trench is formed through the lateral LDD region and partially through the substrate self-aligned to the sidewall spacer. A vertical drift region is formed along a sidewall of the trench. An insulating material is deposited in the trench. A first source region is formed adjacent to the first gate structure opposite the lateral LDD region. A second source region is formed adjacent to the second gate structure opposite the lateral LDD region.Type: ApplicationFiled: May 23, 2012Publication date: November 28, 2013Applicant: GREAT WALL SEMICONDUCTOR CORPORATIONInventors: Zheng John Shen, Patrick M. Shea, David N. Okada
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Publication number: 20130313633Abstract: A semiconductor device has a substrate and trench formed partially through the substrate. A drain region is formed in the substrate as a second surface of the substrate. An epitaxial region is formed in the substrate over the drain region. A vertical drift region is formed along a sidewall of the trench. An insulating material is deposited within the trench. A channel region is formed along the sidewall of the trench above the insulating material. The channel region is separated from the insulating material. A gate structure is formed within the trench adjacent to the channel region. The gate structure includes an insulating layer formed along the sidewall of the trench adjacent to the channel region and polysilicon layer formed within the trench over the insulating layer. A source region is formed in a first surface of the substrate contacting the channel region.Type: ApplicationFiled: May 23, 2012Publication date: November 28, 2013Applicant: GREAT WALL SEMICONDUCTOR CORPORATIONInventors: Zheng John Shen, Patrick M. Shea, David N. Okada
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Publication number: 20120313147Abstract: A semiconductor device has a substrate with a source region and a drain region formed on the substrate. A silicide layer is disposed over the source region and drain region. A first interconnect layer is formed over the silicide layer and includes a first runner connected to the source region and second runner connected to the drain region. A second interconnect layer is formed over the first interconnect layer and includes a third runner connected to the first runner and a fourth runner connected to the second runner. An under bump metallization (UBM) is formed over and electrically connected to the second interconnect layer. A mask is disposed over the substrate with an opening in the mask aligned over the UBM. A conductive bump material is deposited within the opening in the mask. The mask is removed and the conductive bump material is reflowed to form a bump.Type: ApplicationFiled: June 8, 2011Publication date: December 13, 2012Applicant: GREAT WALL SEMICONDUCTOR CORPORATIONInventors: Samuel J. Anderson, David N. Okada
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Publication number: 20120248601Abstract: A semiconductor device has a semiconductor wafer with a plurality of semiconductor die including a plurality of contact pads. An insulating layer is formed over the semiconductor wafer and contact pads. An under bump metallization (UBM) is formed over and electrically connected to the plurality of contact pads. A mask is disposed over the semiconductor wafer with a plurality of openings aligned over the plurality of contact pads. A conductive bump material is deposited within the plurality of openings in the mask and onto the UBM. The mask is removed. The conductive bump material is reflowed to form a plurality of bumps with a height less than a width. The plurality of semiconductor die is singulated. A singulated semiconductor die is mounted to a substrate with bumps oriented toward the substrate. Encapsulant is deposited over the substrate and around the singulated semiconductor die.Type: ApplicationFiled: March 29, 2012Publication date: October 4, 2012Applicant: GREAT WALL SEMICONDUCTOR CORPORATIONInventors: Samuel J. Anderson, Gary Dashney, David N. Okada
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Publication number: 20120205740Abstract: A semiconductor device includes a substrate having a first region and a second region. The first region is electrically isolated from the second region. The semiconductor device further includes a lateral field-effect transistor (FET) disposed within the first region. The lateral FET includes a first terminal and a second terminal. The semiconductor device further includes a diode disposed within the second region, the diode including a plurality of anode regions and a plurality of cathode regions. The semiconductor device further includes a first electrical connection between the first terminal of the lateral FET and the anode regions of the diode, and a second electrical connection between the second terminal of the lateral FET and the cathode regions of the diode. The first and second electrical connections are disposed over a surface of the substrate.Type: ApplicationFiled: December 24, 2010Publication date: August 16, 2012Applicant: GREAT WALL SEMICONDUCTOR CORPORATIONInventors: Samuel J. Anderson, David N. Okada, Gary Dashney, David A. Shumate