Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to calculate and present an output signal having a first resolution in response to (i) an input signal having a second resolution and (ii) one or more control signals. The second circuit may be configured to generate the control signals in response to (i) a previous calculation by the first circuit and (ii) one or more input parameters. The first circuit may be configured to scale and filter the input signal.

Abstract: An apparatus comprising a data modification circuit and a composite circuit. The data modification circuit may be configured to generate a first output data stream in response to a first one or more of the data streams. The composite circuit may be configured to generate a combined output data stream in response to the first output data stream and remaining data streams.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a first portion of an output data stream in response to a first portion of an input data stream. The second circuit may be configured to present a second portion of the output data stream in response to a second portion of the input data stream. The apparatus may be configured to perform color and gamma correction on the input data stream to generate the output data stream in response to one or more control signals. In one example, the apparatus may comprise block move engine (BME).

Abstract: A circuit for reducing the number of bits in a K bit value from K to N bits. The circuit generally comprises a first summing circuit, a control circuit, an error feedback circuit, a second summing circuit, and a processor. The first summing circuit may add an error offset value and the N+m MSB's of the K bit value to produce a result data value. The control circuit may generate a dither offset value. The error feedback circuit may receive m LSBs of the result data value and generate an error value in dependence on the m LSBs. The second summing circuit may add the dither offset value and the error value to provide the error offset value. The processor may selectively control generation of the dither offset value and the error value.

Abstract: A method of performing data shifts in a data processing system between a source and a plurality of destinations using a direct memory accessing scheme, comprising the steps of: (A) reading a data block from the source destinations; (B) writing the data block to a first of the plurality of destinations; and (C) writing the data block to a second of the plurality of destinations. Addresses of the first and second destinations are previously stored.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be conf igured to generate an address signal in response to (i) a first ramp signal, (ii) a second ramp signal, and (iii) a format signal. The second circuit may be configured to generate the first and second ramp signals in response to a one or more control signals. The address signal may support a raster format when the format signal is in a first state and may support a macroblock format when the format signal is in a second state.

Abstract: An apparatus comprising a data modification circuit and a composite circuit. The data modification circuit may be configured to generate a first and second video component in response to a video data stream. The composite circuit may be configured to present an output graphics stream by interleaving the first and the second video component.

Abstract: A method of transferring a block of graphics data for display on a screen along a data bus between a processing block and a plurality of addresses in memory comprising the steps of (A) generating a first and a second X and Y coordinate value for each of one or more portions of data to be transferred, (B) calculating a respective address in memory of the plurality of addresses corresponding to each of the first and second coordinate values, (C) accessing the addresses to effect the data transfer, (D) determining if a plurality of bus criteria are met and (E) enabling or inhibiting transfer of the block of data in a data burst in response to the plurality of criterias being met.

Abstract: A method of performing data shifts in a data processing system between a source and a plurality of destinations using a direct memory accessing scheme, comprising the steps of: (A) reading a data block from the source destinations; (B) writing the data block to a first of the plurality of destinations; and (C) writing the data block to a second of the plurality of destinations. Addresses of the first and second destinations are previously stored.

Abstract: A method of transferring a block of graphics data for display on a screen along a data bus between a processing block and a plurality of addresses in memory comprising the steps of (A) generating a first and a second X and Y coordinate value for each of one or more portions of data to be transferred, (B) calculating a respective address in memory of the plurality of addresses corresponding to each of the first and second coordinate values, (C) accessing the addresses to effect the data transfer, (D) determining if a plurality of bus criteria are met and (E) enabling or inhibiting transfer of the block of data in a data burst in response to the plurality of criterias being met.

Abstract: A circuit for reducing the number of bits in a K bit value from K to N bits. The circuit generally comprises a first summing circuit, a control circuit, an error feedback circuit, a second summing circuit, and a processor. The first summing circuit may add an error offset value and the N+m MSB's of the K bit value to produce a result data value. The control circuit may generate a dither offset value. The error feedback circuit may receive m LSBs of the result data value and generate an error value in dependence on the m LSBs. The second summing circuit may add the dither offset value and the error value to provide the error offset value. The processor may selectively control generation of the dither offset value and the error value.