Patents by Inventor David Naegle

David Naegle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030142099
    Abstract: A graphics system comprising a programmable sample buffer and a sample buffer interface. The sample buffer interface is configured to (a) buffer N streams of samples in N corresponding input buffers, wherein N is greater than or equal to two, (b) store N sets of context values corresponding to the N input buffers respectively, (c) terminate transfer of samples from a first of the input buffers to the programmable sample buffer, (d) selectively update a subset of state registers in the programmable sample buffer with context values corresponding to a next input buffer of the input buffers, (e) initiate transfer of samples from the next input buffer to the programmable sample buffer. The context values stored in the state registers of the programmable sample buffer determine the operation of an arithmetic logic unit internal to the programmable sample buffer on samples data.
    Type: Application
    Filed: January 30, 2002
    Publication date: July 31, 2003
    Inventors: Michael F. Deering, Nathaniel David Naegle, Michael G. Lavelle
  • Publication number: 20030137528
    Abstract: A graphics system that is configured to synchronize a slave display channel to a master display channel may include a master display timing generator configured to provide a frame event indication and a slave display timing generator. The slave display timing generator may be configured to receive the frame event indication and, in response to receiving the frame event indication during its active display period, the slave display timing generator may be configured to wait until its current active display period ends and then jump to its synchronization point. Alternatively, the slave display timing generator may be configured to jump to its synchronization point immediately or after the end of the current horizontal line, and any remaining display information in an interrupted frame may be displayed during the next active display period.
    Type: Application
    Filed: January 4, 2002
    Publication date: July 24, 2003
    Inventors: Michael A. Wasserman, Michael G. Lavelle, Justin Michael Mahan, David Naegle, Glenn J. Gracon
  • Patent number: 6577312
    Abstract: A computer graphics system may comprise a graphics processor, a sample buffer, and a sample-to-pixel calculation unit. The graphics processor renders samples into the sample buffer in response to received graphics data. The sample-to-pixel calculation unit generates a plurality of output pixels by filtering the rendered samples based on a filter function. The pixels may be computed by generating a weighted sum of sample values (e.g. red sample values) for samples falling within the filter support. The coefficients used in the weighted sum may be added to form a normalization factor. One weighted sum of sample values may be computed per pixel attribute such as red, green, blue and alpha. The normalization factor may be computed in parallel with one or more of the weighted sums. Normalized pixel values may be obtained by dividing the weighted-sums by the normalization factor.
    Type: Grant
    Filed: January 4, 2001
    Date of Patent: June 10, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Michael F. Deering, N. David Naegle, Scott R. Nelson
  • Publication number: 20030058247
    Abstract: A video routing system including video routers VR(0), VR(1), . . . , VR(NR−1) coupled in a linear series. Each video router in the linear series successively operates on a digital video stream. Each video router provides a synchronous clock with its output video stream so a link interface buffer in the next video router can capture values from the output video stream in response to the synchronous clock. Each video router buffers a common clock to generate a local output clock. The output clock is used as a read clock to read data out of the corresponding link interface buffer. The output clock is also used to generate the synchronous clock that is transmitted downstream. To initialize the series, reset is sequentially removed from each video router starting from the first video router after the common clock has stabilized.
    Type: Application
    Filed: July 15, 2002
    Publication date: March 27, 2003
    Inventor: Nathaniel David Naegle
  • Publication number: 20030043155
    Abstract: A graphics system that may be shared between multiple display channels includes a frame buffer, two arbiters, a pixel buffer, and several display output queues. The first arbiter arbitrates between the display channels' requests for display information from the frame buffer and forwards a selected request to the frame buffer. The frame buffer outputs display information in response to receiving the forwarded request, and pixels corresponding to this display information are stored in the pixel buffer. Each display channel has a corresponding display output queue that provides data to a display and generates a request for pixels from the pixel buffer. A pixel request arbiter receives the pixel requests generated by the display output queues, selects one of the pixel requests, and forwards the selected request to the pixel buffer. In response, the pixel buffer outputs pixels to the display output queue that generated the selected pixel request.
    Type: Application
    Filed: May 18, 2001
    Publication date: March 6, 2003
    Applicant: Sun Microsystems, Inc.
    Inventors: Michael A. Wasserman, Michael G. Lavelle, David C. Kehlet, Nathaniel David Naegle, Steven Te-Chun Yu, Glenn Gracon
  • Publication number: 20030020709
    Abstract: A computer graphics system that utilizes a super-sampled sample buffer and a sample-to-pixel calculation unit for refreshing the display. The graphics system may have a graphics processor, a super-sampled sample buffer, and a sample-to-pixel calculation unit. The graphics processor renders samples into the sample buffer and may utilize a window ID that specifies attributes of pixels on a per object basis. The window ID may specify one or more of a sample mode, filter type, color attributes, or source attributes. The sample mode may include single sample per pixel mode and multiple samples per pixel mode. The graphics system may be further operable to generate a single sample per pixel for certain windows of the screen in order to provide backwards compatibility with legacy systems.
    Type: Application
    Filed: July 12, 2002
    Publication date: January 30, 2003
    Applicant: Sun Microsystems, Inc.
    Inventors: Nathaniel David Naegle, Michael F. Deering, Michael G. Lavelle, Carol A. Lavelle, Scott R. Nelson
  • Publication number: 20030011609
    Abstract: A graphics system comprising a control unit and a series of calculation units coupled together in a closed chain by a segmented communication bus. The calculation unit collaboratively generate one or more video signals. Each calculation unit is programmably assigned to contribute its locally-generated pixels to one of the video streams. The control unit sends a frame readback request to a selected one of the calculation units through the segmented communication bus. The frame readback request specifies some subset of the pixels in one of the video streams for readback to the control unit. In response to the frame readback request, the selected calculation unit transmits the subset of pixels of the specified video stream to the control unit, and the control unit forwards the subset of pixels to a target memory block (e.g. in system memory of a host computer or memory within the graphics system).
    Type: Application
    Filed: June 28, 2001
    Publication date: January 16, 2003
    Inventors: Michael F. Deering, Nathaniel David Naegle
  • Patent number: 6496187
    Abstract: A graphics system that is configured to utilize a sample buffer and a plurality of parallel sample-to-pixel calculation units, wherein the sample-pixel calculation units are configured to access different portions of the sample buffer in parallel. The graphics system may include a graphics processor, a sample buffer, and a plurality of sample-to-pixel calculation units. The graphics processor is configured to receive a set of three-dimensional graphics data and render a plurality of samples based on the graphics data. The sample buffer is configured to store the plurality of samples for the sample-to-pixel calculation units, which are configured to receive and filter samples from the sample buffer to create output pixels. Each of the sample-to-pixel calculation units are configured to generate pixels corresponding to a different region of the image. The region may be a vertical or horizontal stripe of the image, or a rectangular portion of the image.
    Type: Grant
    Filed: December 27, 1999
    Date of Patent: December 17, 2002
    Assignee: Sun Microsystems, Inc.
    Inventors: Michael F. Deering, Nathaniel David Naegle, Scott R. Nelson
  • Patent number: 6424343
    Abstract: A method and computer graphics system capable of super-sampling and performing programmable real-time filtering or convolution are disclosed. In one embodiment, the computer graphics system may comprise a graphics processor, a sample buffer, and a sample-to-pixel calculation unit. The graphics processor may be configured to generate a plurality of samples. The sample buffer, which is coupled to the graphics processor, is configured to store the samples and may be configured to double-buffer at least part of the stored samples. The sample-to-pixel calculation unit is programmable to select a variable number of stored samples from the sample buffer to filter into an output pixel. The sample-to-pixel calculation unit performs the filter process in real-time, and may be programmable to use a number of different filter types in.a single frame. The sample buffer may be super-sampled, and the samples may be positioned according to a regular grid, a perturbed regular grid, or a stochastic grid.
    Type: Grant
    Filed: February 17, 1999
    Date of Patent: July 23, 2002
    Assignee: Sun Microsystems, Inc.
    Inventors: Michael F. Deering, David Naegle, Scott Nelson
  • Patent number: 6417861
    Abstract: A method and computer graphics system for rendering images using programmable sample positions is disclosed. In one embodiment, the computer graphics system may comprise a graphics processor, a sample buffer, and a sample-to-pixel calculation unit. The graphics processor may be configured to generate a plurality of samples using a sample positioning algorithm selected from a programmable memory or generated by programmable hardware. The sample buffer, which is coupled to the graphics processor, may be configured to store the samples. The sample buffer may be super-sampled and double buffered. The sample-to-pixel calculation unit is programmable to select a variable number of stored samples from the sample buffer to filter into an output pixel. The sample-to-pixel calculation unit performs the filter process in real-time, and may use a number of different filter types.
    Type: Grant
    Filed: February 17, 1999
    Date of Patent: July 9, 2002
    Assignee: Sun Microsystems, Inc.
    Inventors: Michael F. Deering, Nathaniel David Naegle, Scott Nelson
  • Publication number: 20020033828
    Abstract: A graphics system comprising a series of calculation units. The calculation units comprise a first subset and a second subset of calculation units. A first calculation unit of the series generates a first digital video stream and a second digital video stream. Each calculation unit of the first subset: (a) passes the second digital video stream to a next calculation unit of the series unmodified; and (b) computes first pixel values, injects or mixes the first pixel values into the first digital video stream, and passes the modified first digital video stream to the next calculation unit. Similarly, each calculation unit of the second subset injects or mixes second pixel values into the second digital video stream, and passes the first digital video stream unmodified. A last calculation unit of the series drives one or more display devices in response to the first and second digital video streams.
    Type: Application
    Filed: June 27, 2001
    Publication date: March 21, 2002
    Inventors: Michael F. Deering, N. David Naegle
  • Publication number: 20020015041
    Abstract: A sample-to-pixel calculation unit in a graphics system may comprise an adder tree. The adder tree includes a plurality of adder cells coupled in a tree configuration. Input values are presented to a first layer of adder cells. Each input value may have two associated control signals: a data valid signal and a winner-take all signal. The final output of the adder tree equals (a) a sum of those input values whose data valid signals are asserted provided that none of the winner-take all signals are asserted, or (b) a selected one of the input values if one of the winner-take-all bits is asserted. The selected input value is the one whose winner-take-all bit is set. The adder tree may be used to perform sums of weighted sample attributes and/or sums of coefficients values as part of pixel value computations.
    Type: Application
    Filed: June 28, 2001
    Publication date: February 7, 2002
    Inventors: N. David Naegle, Scott R. Nelson
  • Publication number: 20020005854
    Abstract: A dithering system comprising a dithering unit, a storage medium, and an averaging unit. The dithering unit is configured to receive a set of data values, to add dither values to the data values, and to truncate the resultant addition values to L-bit truncated values. The storage medium is configured to store the L-bit truncated values. The averaging unit is configured to read the L-bit truncated values from the storage medium, and to compute an average value using at least a subset of the L-bit truncated values. The dither values may have an average value of approximately one-half. The dither values may approximate a uniform distribution of numbers between −A+½ and A+½, wherein A is greater than or equal to one. Alternatively, the dithering unit may receive a temporal stream of data values, and the average unit may perform a temporal average (e.g. an FIR filter). The dithering system may be incorporated in a graphics system.
    Type: Application
    Filed: January 11, 2001
    Publication date: January 17, 2002
    Applicant: Sun Microsystems, Inc.
    Inventors: Michael F. Deering, N David Naegle, Scott R. Nelson
  • Publication number: 20010055025
    Abstract: A computer graphics system may comprise a graphics processor, a sample buffer, and a sample-to-pixel calculation unit. The graphics processor renders samples into the sample buffer in response to received graphics data. The sample-to-pixel calculation unit generates a plurality of output pixels by filtering the rendered samples based on a filter function. The pixels may be computed by generating a weighted sum of sample values (e.g. red sample values) for samples falling within the filter support. The coefficients used in the weighted sum may be added to form a normalization factor. One weighted sum of sample values may be computed per pixel attribute such as red, green, blue and alpha. The normalization factor may be computed in parallel with one or more of the weighted sums. Normalized pixel values may be obtained by dividing the weighted-sums by the normalization factor.
    Type: Application
    Filed: January 4, 2001
    Publication date: December 27, 2001
    Applicant: Sun Microsystems, Inc.
    Inventors: Michael F. Deering, N. David Naegle, Scott R. Nelson
  • Publication number: 20010033287
    Abstract: A computer graphics system that utilizes a super-sampled sample buffer and a sample-to-pixel calculation unit for refreshing the display. The graphics system may have a graphics processor, a super-sampled sample buffer, and a sample-to-pixel calculation unit. The graphics processor renders samples into the sample buffer and may utilize a window ID that specifies attributes of pixels on a per object basis. The window ID may specify one or more of a sample mode, filter type, color attributes, or source attributes. The sample mode may include single sample per pixel mode and multiple samples per pixel mode. The graphics system may be further operable to generate a single sample per pixel for certain windows of the screen in order to provide backwards compatibility with legacy systems.
    Type: Application
    Filed: December 29, 2000
    Publication date: October 25, 2001
    Applicant: Sun Microsystems, Inc.
    Inventors: N. David Naegle, Scott R. Nelson, Michael F. Deering
  • Publication number: 20010028352
    Abstract: A computer graphics system that utilizes a super-sampled sample buffer and a sample-to-pixel calculation unit for refreshing the display. The graphics system may have a graphics processor, a super-sampled sample buffer, and a sample-to-pixel calculation unit. The graphics processor renders samples into the sample buffer at computed positions or locations in the sample buffer. The graphics system may utilize a window ID that specifies attributes of pixels on a per object basis. The window ID may specify one or more of a sample mode, filter type, color attributes, or source attributes. The sample mode may include single sample per pixel mode and multiple samples per pixel mode. In implementing a single sample per pixel mode, the graphics system may be further operable to generate a single sample per pixel for certain windows of the screen in order to, for example, provide backwards compatibility with legacy systems with no multi-sampling support.
    Type: Application
    Filed: December 29, 2000
    Publication date: October 11, 2001
    Inventors: N. David Naegle, Michael F. Deering, Michael G. Lavelle, Carol Lavelle, Scott R. Nelson
  • Patent number: 5411405
    Abstract: An apparatus for receiving an RJ series plug and making electrical connection with at the contacts on the plug and conveying any signals on the contacts to a communications device such as a telephone, facsimile machine, modem, or a local area network adapter. A body includes one or more recesses which receive the plug. An expandable and stretchable membrane isolates the contacts in the plug from electrical contact with an object in a surrounding environment such that passage of current from one or more of the electrical contacts to an object present in the surrounding environment is prevented. A removable shell is provided into which the body is slidably held within the communications device. The removable shell allows the shell and the body to be easily replaced. Another body can be pivotally attached to the communications device such that the body is rotated into and out of the communications device for storage and use.
    Type: Grant
    Filed: November 12, 1993
    Date of Patent: May 2, 1995
    Assignee: Angia Communications, Inc.
    Inventors: Steve R. McDaniels, Paul H. Glad, David Naegle, Jon R. Hinto