Abstract: A method and apparatus for socket-based design with reusable intellectual property (IP) includes a chip integration system (CIS) that provides designers with a convenient method to create and describe a system on a chip (SOC) design independent of design flow. A Chip Integration Description Language (CIDL) is also disclosed that provides a mechanism for defining interfaces between IP cores in a way that isolates a system designer from much of the connection information previously required is also disclosed. Using CIDL, a system designer is able to rapidly connect multiple blocks of intellectual property (IP) based upon the functionality of the blocks rather than traditional hardware-specific connection methods. The details pertaining to specific connections that may be needed are encapsulated within a CIDL-based file that is typically written by the IP core designer. The actual connection of signals between blocks of IP, however, is performed by a CIDL compiler that uses the CIDL file(s) as input.

Abstract: The invention provides a knowledge management system particularly suited for use in the integrated circuit design environment. The system allows administrators to define standardized component types. Instantiated components versions comprise “deliverables” and “attributes.” Deliverables comprise a file or directory of files or groups of files or directories that perform a common function and are characterized by the system in a standardized manner. Attributes comprise metadata describe the component version. By the abstraction of design files into deliverables, the systems can work with design files originating from any source and having different structures and still make those design files available by other designers in a uniform manner for efficient reuse of pre-qualified components. Tasks in the design flow can be tracked in the system. The system may also include a communications application, an issue tracking application, and an audit trail application.