Abstract: A memory subsystem includes a first memory, a second memory, a first compressor, and a first decompressor. The first memory is configured to store instruction bytes of a fetch window and to store first predecode information and first branch information that characterizes the instruction bytes of the fetch window. The second memory is configured to store the instruction bytes of the fetch window upon eviction of the instruction bytes from the first memory and to store combined predecode/branch information that also characterizes the instruction bytes of the fetch window. The first compressor is configured to compress the first predecode information and the first branch information into the combined predecode/branch information.

Abstract: A memory subsystem includes a first memory, a second memory, a first compressor, and a first decompressor. The first memory is configured to store instruction bytes of a fetch window and to store first predecode information and first branch information that characterizes the instruction bytes of the fetch window. The second memory is configured to store the instruction bytes of the fetch window upon eviction of the instruction bytes from the first memory and to store combined predecode/branch information that also characterizes the instruction bytes of the fetch window. The first compressor is configured to compress the first predecode information and the first branch information into the combined predecode/branch information.

Abstract: In accordance with a specific embodiment of the present disclosure, hardware periodically monitors a fetch cycle that fetches data associated with an address to determine performance parameters associated with the fetch cycle. Information related to the duration of a fetch cycle is maintained as well as information indicating the occurrence of various states and data values related to the fetch cycle. For example, the virtual address being processed during the fetch cycle is saved at the integrated circuit containing the fetch engine. Other performance-related parameters associated with execution of instructions at an execution engine of the pipeline are also monitored periodically. However, monitoring performance of the fetch engine is decoupled from monitoring performance-related events of the execution engine.

Abstract: A first and second integrated circuit contain respectively a first and second portion of a parallel port, the first portion includes control, configuration, data and status registers and the second portion includes parallel port input and output terminals. A bus couples the first and second integrated circuits and transfers parallel port control and data information between the first and second integrated circuits. The bus includes a clock line providing a clock signal. The bus also includes a data out line that serially transfers output control and data bits from the first to the second integrated circuit, the data and control bits to be provided to the parallel port output terminals on the second integrated circuit. The bus also includes a data in line providing input data and control information from the terminals of the parallel port to the first integrated circuit.

Abstract: A first and a second local interrupt controller are disposed on a single integrated circuit. The first and second local interrupt controllers are coupled to controllably provide at least one interrupt request signal, respectively, to a first and second processor. An input/output (I/O) interrupt controller is also on the integrated circuit and coupled to receive an interrupt request from at least one input/output device. A communication circuit on the integrated circuit is coupled to the input/output interrupt controller and the first and second local interrupt controllers. The communication circuit provides for transfer of interrupt information between the first local interrupt controller, the second local interrupt controller and the input/output interrupt controller.