Patents by Inventor David Nguyen
David Nguyen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20050079101Abstract: Sample processing devices that include transmissive layers and control layers to reduce or eliminate cross-talk between process chambers in the processing device are disclosed. The transmissive layers may transmit significant portions of signal light and/or interrogation light while the control layers block significant portions of signal light and/or interrogation light. Methods of manufacturing processing devices that include transmissive layers and control layers are also disclosed. The methods may involve continuous forming processes including co-extrusion of materials to form the transmissive layer and control layer in a processing device, followed by formation of the process chambers in the control layer. Alternatively, the methods may involve extrusion of materials for the control layer, followed by formation of process chambers in the control layer.Type: ApplicationFiled: October 9, 2003Publication date: April 14, 2005Inventors: Joel Dufresne, Bryan Feisel, Theresa Gerten, Brent Hansen, David Nguyen
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Publication number: 20050073294Abstract: A current control circuit that employs a magnetic amplifier and an active feedback circuit. The feedback circuit establishes the effective operating current of the amplifier at a fixed point. The magnetic amplifier includes a pair of oppositely wound gate windings, a bias winding and a control winding. The gate windings are driven by an oscillator driver that generates a gate winding current and a gate winding voltage. A reference voltage and the gate winding voltage are applied to a feedback amplifier and the feedback circuit. When the gate winding voltage becomes equal to the reference voltage, the feedback circuit is stable and the gate winding current is set to a desired zero current operating point.Type: ApplicationFiled: October 7, 2003Publication date: April 7, 2005Applicant: Northrop Grumman CorporationInventors: Donald Baxter, Kenneth Wheeler, David Nguyen
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Publication number: 20050068082Abstract: A method and apparatus for accommodating delay variations among multiple signals are provided. According to one embodiment of the invention, transitions of one or more of a plurality of lines between different levels are detected. The timing of a signal affecting recovery of information from the plurality of lines is adjusted according to the transitions detected. Examples of such a signal include one or more signals carried on one or more of the plurality of lines and a timing signal carried on a line separate from the plurality of lines.Type: ApplicationFiled: October 15, 2004Publication date: March 31, 2005Inventors: David Nguyen, Suresh Rajan
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Patent number: 6868474Abstract: A memory device includes an interconnect with mask pins and a memory core for storing data. A memory interface circuit is connected between the interconnect and the memory core. The memory interface circuit selectively processes write mask data from the mask pins or precharge instruction signals from the mask pins.Type: GrantFiled: April 22, 2002Date of Patent: March 15, 2005Assignee: Rambus Inc.Inventors: Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar, James A. Gasbarro, David Nguyen
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Publication number: 20040221083Abstract: A high frequency bus system which insures uniform arrival times of high-fidelity signals to the devices on the high frequency bus, despite the use of the bus on modules and connectors. A high frequency bus system includes a first bus segment having one or more devices connected between a first and a second end. The first bus segment has at least a pair of transmission lines for propagating high frequency signals and the devices are coupled to the pair of transmission lines. The high frequency bus system also includes a second bus segment which has no devices connected to it. The second bus segment also has at least a pair of transmission lines for propagating high frequency signals. The first end of the first segment and second end of the second segment are coupled in series to form a chain of segments and when two signals are introduced to the first end of the second bus segment at the substantially the same time, they arrive at each device connected to the first bus segment at substantially the same time.Type: ApplicationFiled: April 19, 2001Publication date: November 4, 2004Applicant: RAMBUS INC.Inventors: Haw-Jyh Liaw, David Nguyen
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Publication number: 20040164393Abstract: The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dice positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dice. The programmable memory device is programmable to identify the integrated circuit dice that meet a predetermined standard, such as an operating frequency requirement, or a core timing grade. Further, a method is provided for accessing a semiconductor module. The above mentioned housing is provided to enclose the plurality of integrated circuit dice and the programmable memory device. The integrated circuit dice of the plurality of integrated circuit dice that meet a predetermined standard are then identified. The programmable memory device is subsequently programmed to identify the selected integrated circuit dice.Type: ApplicationFiled: February 20, 2004Publication date: August 26, 2004Applicant: Rambus, Inc.Inventors: Thomas F. Fox, Sayeh Khalili, Belgacem Haba, David Nguyen, Richard Warmke, Xingchao Yuan
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Patent number: 6765800Abstract: Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.Type: GrantFiled: April 20, 2001Date of Patent: July 20, 2004Assignee: Rambus Inc.Inventors: Belgacem Haba, Richard E. Perego, David Nguyen, Billy W. Garrett, Jr., Ely Tsern, Craig E. Hampel, Wai-Yeung Yip
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Publication number: 20040105240Abstract: Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.Type: ApplicationFiled: October 30, 2003Publication date: June 3, 2004Applicant: Rambus Inc.Inventors: Belgacem Haba, Richard E. Perego, David Nguyen, Billy W. Garrett, Ely Tsern, Craig E. Hampel, Wai-Yeung Yip
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Patent number: 6720643Abstract: The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dies positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dies. The programmable memory device is programmable to identify the integrated circuit dies that meet a predetermined standard, such as an operating frequency requirement, or a core timing grade. Further, a method is provided for accessing a semiconductor module. The above mentioned housing is provided to enclose the plurality of integrated circuit dies and the programmable memory device. The integrated circuit dies of the plurality of integrated circuit dies that meet a predetermined standard are then identified. The programmable memory device is subsequently programmed to identify the selected integrated circuit dies.Type: GrantFiled: February 22, 2001Date of Patent: April 13, 2004Assignee: Rambus, Inc.Inventors: Thomas F. Fox, Sayeh Khalili, Belgacem Haba, David Nguyen, Richard Warmke, Xingchao Yuan
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Publication number: 20040066636Abstract: An apparatus is provided, which includes a memory interface circuit, a clock signal generating circuit, and a plurality of memory circuits. The memory circuits are operatively coupled and arranged in an order on a plurality of memory modules, such that the memory module positioned at the beginning of the order is coupled to an output of the clock signal generating circuit and the memory interface circuit. The memory module that is positioned at the end of the order is unique in that it includes a clock signal terminating circuit connected to the last memory integrated circuit. With this configuration, a clock loop is formed by directly routing the clock signal from the output of the clock signal generating circuit through each of the memory modules in the order (without connecting to any of the intervening memory integrated circuits) to the memory integrated circuit positioned at the end of the order.Type: ApplicationFiled: April 22, 2003Publication date: April 8, 2004Inventors: Ravindranath T. Kollipara, David Nguyen, Belgacem Haba
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Patent number: 6590781Abstract: An apparatus is provided, which includes a memory interface circuit, a clock signal generating circuit, and a plurality of memory circuits. The memory circuits are operatively coupled and arranged in an order on a plurality of memory modules, such that the memory module positioned at the beginning of the order is coupled to an output of the clock signal generating circuit and the memory interface circuit. The memory module that is positioned at the end of the order is unique in that it includes a clock signal terminating circuit connected to the last memory integrated circuit. With this configuration, a clock loop is formed by directly routing the clock signal from the output of the clock signal generating circuit through each of the memory modules in the order (without connecting to any of the intervening memory integrated circuits) to the memory integrated circuit positioned at the end of the order.Type: GrantFiled: March 26, 2001Date of Patent: July 8, 2003Assignee: Rambus, Inc.Inventors: Ravindranath T. Kollipara, David Nguyen, Belgacem Haba
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Method and apparatus to provide dynamic ultrasonic measurement of rolling element bearing parameters
Patent number: 6571632Abstract: An acoustic signal unit comprises a signal generation unit to generate a first electrical signal, a first transducer to generate an acoustic signal in response to the first electrical signal, and a second transducer to generate a second electrical signal in response to the received acoustic signal. A calculation unit is provided to compare the first and second electrical signals to determine the time of flight of the acoustic signal, wherein the time of flight corresponds to the stress in the rolling element bearing. The stress may be calculated according to a formula or by multiplying an acoustic time constant for the rolling element bearing by the distance traveled by the acoustic signal across the rolling element bearing, and by the time of flight determined by said comparison unit.Type: GrantFiled: May 18, 2000Date of Patent: June 3, 2003Assignee: The Torrington CompanyInventors: Richard W. Browner, Richard L. Lemoine, Mark I. Jurras, III, David Nguyen, Robert Domnitz, Alan Robert Selfridge -
Publication number: 20020178324Abstract: A memory device includes an interconnect with mask pins and a memory core for storing data. A memory interface circuit is connected between the interconnect and the memory core. The memory interface circuit selectively processes write mask data from the mask pins or precharge instruction signals from the mask pins.Type: ApplicationFiled: April 22, 2002Publication date: November 28, 2002Applicant: Rambus Inc.Inventors: Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar, James A. Gasbarro, David Nguyen
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Publication number: 20020136214Abstract: A pervasive computing network is disclosed including a group of first access controllers connected together on a first local area network, with each of the first access controllers including a radio frequency transceiver constructed to transmit and receive radio frequency signals within a range less than about 100 meters and wherein at least two of the ranges of the first access controllers overlap one another and the first access controllers are constructed to communicate with a consumer touchpoint device. The pervasive computing network further includes a group of second access controllers connected together on a second local area network, each of the second access controllers including a radio frequency transceiver constructed to transmit and receive radio frequency signals within a range less than about 100 meters, with at least two of the ranges of the second access controllers overlapping one another and the second access controllers being constructed to communicate with the consumer touchpoint device.Type: ApplicationFiled: August 14, 2001Publication date: September 26, 2002Applicant: Consumer Direct LinkInventors: Cuong D. Do, David Nguyen, Lan Nguyen, Nhut T. Ha, Tudo D. Do
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Patent number: 6401167Abstract: A memory device includes an interconnect with mask pins and a memory core for storing data. A memory interface circuit is connected between the interconnect and the memory core. The memory interface circuit selectively processes write mask data from the mask pins or precharge instruction signals from the mask pins.Type: GrantFiled: October 9, 1998Date of Patent: June 4, 2002Assignee: Rambus IncorporatedInventors: Richard M. Barth, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar, James A. Gasbarro, David Nguyen
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Publication number: 20010053069Abstract: Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.Type: ApplicationFiled: April 20, 2001Publication date: December 20, 2001Applicant: Rambus Inc.Inventors: Belgacem Haba, Richard E. Perego, David Nguyen, Billy W. Garrett, Ely Tsern, Craig E. Hampel, Wai-Yeung Yip
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Publication number: 20010040796Abstract: An apparatus is provided, which includes a memory interface circuit, a clock signal generating circuit, and a plurality of memory circuits. The memory circuits are operatively coupled and arranged in an order on a plurality of memory modules, such that the memory module positioned at the beginning of the order is coupled to an output of the clock signal generating circuit and the memory interface circuit. The memory module that is positioned at the end of the order is unique in that it includes a clock signal terminating circuit connected to the last memory integrated circuit. With this configuration, a clock loop is formed by directly routing the clock signal from the output of the clock signal generating circuit through each of the memory modules in the order (without connecting to any of the intervening memory integrated circuits) to the memory integrated circuit positioned at the end of the order.Type: ApplicationFiled: March 26, 2001Publication date: November 15, 2001Inventors: Ravindranath T. Kollipara, David Nguyen, Belgacem Haba
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Patent number: 6287132Abstract: A connector with a staggered contact design is described. The connector comprises a first row of connector pins, the connector pins alternately proximal pins and distal pins. The connector further comprises a second row of connector pins alternately proximal pins and distal pins. The distal pins of the connector carry the signals, while the proximal pins are ground or power signals.Type: GrantFiled: May 22, 2000Date of Patent: September 11, 2001Assignee: Rambus Inc.Inventors: Donald Perino, David Nguyen
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Patent number: 6266730Abstract: A high frequency bus system which insures uniform arrival times of high-fidelity signals to the devices on the high frequency bus, despite the use of the bus on modules and connectors. A high frequency bus system includes a first bus segment having one or more devices connected between a first and a second end. The first bus segment has at least a pair of transmission lines for propagating high frequency signals and the devices are coupled to the pair of transmission lines. The high frequency bus system also includes a second bus segment which has no devices connected to it. The second bus segment also has at least a pair of transmission lines for propagating high frequency signals. The first end of the first segment and second end of the second segment are coupled in series to form a chain of segments and when two signals are introduced to the first end of the second bus segment at the substantially the same time, they arrive at each device connected to the first bus segment at substantially the same time.Type: GrantFiled: February 18, 2000Date of Patent: July 24, 2001Assignee: Rambus Inc.Inventors: Donald V. Perino, Billy Wayne Garrett, Jr., Haw-Jyh Liaw, David Nguyen, Srinivas Nimmagadda, James A. Gasbarro, Richard DeWitt Crisp
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Patent number: 6160716Abstract: A connector with a staggered contact design is described. The connector comprises a first row of connector pins, the connector pins alternately proximal pins and distal pins. The connector further comprises a second row of connector pins alternately proximal pins and distal pins. The distal pins of the connector carry the signals, while the proximal pins are ground or power signals.Type: GrantFiled: June 25, 1999Date of Patent: December 12, 2000Assignee: Rambus IncInventors: Donald Perino, David Nguyen