Abstract: A single chip multiprocessor interface device for interfacing between two processors by connection to their bus systems, the device having a random access memory selectively accessible by the processors under the control of an arbitration latch. The arbitration latch has a bistable device the state of which determines which processor has access to the memory. The outputs of the bistable device have threshold devices which have threshold levels higher than the signal outputs of the bistable device when it is in a metastable state, so that there is no possibility that both processors could have access to the memory at the same time. Data and address registers for the two processors are selectively connectible to the random access memory through multiplexers controlled by the arbitration latch.