Abstract: New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new logic block is a tree structure comprised of a number of levels of cells with each cell consisting of a logic gate or the functional equivalent of a logic gate, one or more selectable inverters, and wherein the inputs of the logic block consist of the inputs to the logic gate or functional equivalent of the logic gate and inputs to the selectable inverters. The new logic blocks can map circuits more efficiently than LUTs, because they include multi-output blocks and can cover more logic depth due to the higher input and output bandwidth.

Abstract: New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new logic block is a tree structure comprised of a number of levels of cells with each cell consisting of a logic gate or the functional equivalent of a logic gate, one or more selectable inverters, and wherein the inputs of the logic block consist of the inputs to the logic gate or functional equivalent of the logic gate and inputs to the selectable inverters. The new logic blocks can map circuits more efficiently than LUTs, because they include multi-output blocks and can cover more logic depth due to the higher input and output bandwidth.

Abstract: New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new logic block is an AND-Inverter Cone (AIC), which is a binary tree including one or more AND gates with a programmable conditional inversion and a number of intermediary outputs. Compared to LUTs, AICs are richer in terms of input and output bandwidth, because the area of the AICs grows only linearly with the number of inputs. Also, the delay grows only logarithmically with the input count. The new logic blocks can map circuits more efficiently than LUTs, because the AICs are multi-output blocks and can cover more logic depth due to the higher input bandwidth.

Abstract: A method and device for converting first program code into second program code, such that the second program code has an improved execution on a targeted programmable platform, is disclosed. In one aspect, the method includes grouping operations on data for joint execution on a functional unit of the targeted platform, scheduling operations on data in time, and assigning operations to an appropriate functional unit of the targeted platform. Detailed word length information, rather than the typically used approximations like powers of two, may be used in at least one of the grouping, scheduling or assigning operations.

Abstract: Systems and methods for obtaining fluorochrome abundance information by unmixing fluorescence emission data captured by a flow cytometer in accordance with embodiments of the invention are disclosed. In one embodiment, a data analysis system includes a processor, a memory, and an optical data analysis application, wherein the optical data analysis application configures the processor to obtain control optical data, generate a mixing model using the obtained control optical data and a system of linear combinations, obtain experimental optical data for particles stained with a set of fluorochromes, and estimate abundances of the fluorochromes in the set of fluorochromes using the obtained experimental optical data by solving a system of equations to unmix the optical data, where the number of equations is larger than the number of unknowns, based upon the generated mixing model using an unmixing process that accounts for increased noise variance with increased fluorochrome abundance.

Abstract: New logic blocks capable of replacing the use of Look-Up Tables (LUTs) in integrated circuits, such as Field-Programmable Gate Arrays (FPGAs), are disclosed herein. In one embodiment, the new logic block is an AND-Inverter Cone (AIC), which is a binary tree including one or more AND gates with a programmable conditional inversion and a number of intermediary outputs. Compared to LUTs, AICs are richer in terms of input and output bandwidth, because the area of the AICs grows only linearly with the number of inputs. Also, the delay grows only logarithmically with the input count. The new logic blocks can map circuits more efficiently than LUTs, because the AICs are multi-output blocks and can cover more logic depth due to the higher input bandwidth.

Abstract: Electronic publication systems are disclosed that enable the analysis and publication of layout files, which contain an analysis strategy and embedded raw data. The published layout files can be accessed by reader applications that are able to read the layout files and modify the analysis strategy within the layout file using the embedded raw data. In many embodiments, the reader applications are unable to access the embedded raw data. In several embodiments, the reader applications prevent the saving or printing of layout files.

Abstract: A method for determining a data format for processing data to be transmitted along a communication path is disclosed. In one aspect, the method includes identifying at run-time an operational configuration based on received information on the conditions for communication on the communication path. The method may also include selecting according to the identified operational configuration, a data format for processing data to be transmitted among a plurality of predetermined data formats.

Abstract: A method and device for converting first program code into second program code, such that the second program code has an improved execution on a targeted programmable platform, is disclosed. In one aspect, the method includes grouping operations on data for joint execution on a functional unit of the targeted platform, scheduling operations on data in time, and assigning operations to an appropriate functional unit of the targeted platform. Detailed word length information, rather than the typically used approximations like powers of two, may be used in at least one of the grouping, scheduling or assigning operations.

Abstract: Electronic publication systems are disclosed that enable the analysis and publication of layout files, which contain an analysis strategy and embedded raw data. The published layout files can be accessed by reader applications that are able to read the layout files and modify the analysis strategy within the layout file using the embedded raw data. In many embodiments, the reader applications are unable to access the embedded raw data. In several embodiments, the reader applications prevent the saving or printing of layout files. One embodiment of the invention includes a publication computer connected to a network, a user computer connected to the network and the publication computer is configured to generate a file including an analysis strategy based on the raw data and in which the raw data is embedded.