Patents by Inventor David Nozadze

David Nozadze has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250261301
    Abstract: A device is provided that includes a printed circuit board having a top surface, a first trace disposed directly on the top surface of the printed circuit board, and a second trace disposed directly on the top surface of the printed circuit board adjacent the first trace. A first metal dome is positioned over the first trace and is configured to block crosstalk between the first trace and the second trace.
    Type: Application
    Filed: February 9, 2024
    Publication date: August 14, 2025
    Inventors: Mike Sapozhnikov, Joel Richard Goergen, David Nozadze, Amendra Koul, Sayed Ashraf Mamun, Upen Reddy Kareti
  • Publication number: 20250240870
    Abstract: A design and process address power delivery problems for PTH and one-step HDI designs. In some implementations, the quantity of layers may be reduced and the thickness of the board may be reduced. In one embodiment, a PCB is back drilled and a round cap plating is performed to get a more uniform power plane. In one implementation, the back drilled section of a VIA is plated as well, which provides a much bigger shape that is plated for power delivery.
    Type: Application
    Filed: February 29, 2024
    Publication date: July 24, 2025
    Inventors: Wenbin Ma, Mingjian Gao, Weiying Ding, Mingtong Zuo, Yuqing Zhu, Mike Sapozhnikov, Shuo Zhang, David Nozadze
  • Publication number: 20250240873
    Abstract: A multi-lamination stack up structure that separates high speed routing and the power delivery plane. The multi-lamination stack up structure includes M+N layers. The M layers are located on the top of the PCB and focus on high speed design routing. The N layers are located on the bottom of the PCB and are used for the power plane. In one implementation, the PCB uses a through hole or VIA for M+N layers power connection at the chip ball grid array area.
    Type: Application
    Filed: January 19, 2024
    Publication date: July 24, 2025
    Inventors: Wenbin Ma, Weiying Ding, Mike Sapozhnikov, David Nozadze, Joel Richard Goergen, Yuqing Zhu, Mingtong Zuo
  • Publication number: 20250212319
    Abstract: In some aspects, the techniques described herein relate to a printed circuit board, comprising a layer, a first trace coupled to the layer and carrying a first signal; a second trace coupled to the layer and carrying a second signal; and a loss introducing feature that creates an additional signal loss in one of the first trace or the second trace, wherein the additional signal loss balances a first signal loss and a second signal loss.
    Type: Application
    Filed: December 22, 2023
    Publication date: June 26, 2025
    Inventors: Mike Sapozhnikov, Joel Richard Goergen, David Nozadze, Amendra Koul, Upen Reddy Kareti, Sayed Ashraf Mamun
  • Publication number: 20250151198
    Abstract: Techniques to move high current power distribution layers for integrated circuit core power and serializer-deserializer (SERDES) power into a center area of the integrated circuit footprint. This provides a more reliable and higher current distribution into the center of a large integrated circuit footprint, without causing disruption of high speed signal routing or increased signal integrity burden to the high speed signals. Arrangements and methods for routing out the core power area of a main printed circuit board under an integrated circuit and replacing it with a custom power printed circuit board (power plug) that is attached by a metalized paste sintering process. This provides a more reliable and higher current distribution into the center of a large integrated circuit or other high-power component, without causing disruption of high speed signal routing.
    Type: Application
    Filed: February 7, 2024
    Publication date: May 8, 2025
    Inventors: Joel Richard Goergen, Elizabeth Kochuparambil, Scott Hinaga, Kameron Rose Hurst, Mike Sapozhnikov, Shobhana Punjabi, David Nozadze, Marco Croci
  • Publication number: 20250140447
    Abstract: Techniques are provided to mitigate serializer-deserializer performance limiting positive/negative (P/N) skew issues in high-speed cable channels. This may be achieved by adding stripes with low/high dielectric constant (dk) material compared to the main dielectric surrounding cable wires. By adding strips/stripes in the main dielectric, a non-homogeneous dielectric structure is created, and this results in greater coupling between the signal conductors in the cable, which in turn reduces skew impact. This may be useful in twinaxial cables as well as stripline printed circuit boards.
    Type: Application
    Filed: January 22, 2024
    Publication date: May 1, 2025
    Inventors: Mike Sapozhnikov, Amendra Koul, David Nozadze, Joel Richard Goergen, Sayed Ashraf Mamun, Upen Reddy Kareti
  • Patent number: 12289831
    Abstract: A structure includes a first copper layer and a first carbon layer applied directly to a surface of the first copper layer, a second copper layer and a second carbon layer applied directly to a surface of the second copper layer, and an insulating core disposed between the first and second copper layers. Each of the first carbon layer and the second carbon layer faces toward and directly contacts the insulating core. The structure provides electrical power to a component of an electronic device.
    Type: Grant
    Filed: April 24, 2023
    Date of Patent: April 29, 2025
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Joel Goergen, Jessica Kiefer, Alpesh Umakant Bhobe, Kameron Rose Hurst, D. Brice Achkir, Amendra Koul, Scott Hinaga, David Nozadze
  • Publication number: 20250133652
    Abstract: In some embodiments, an apparatus includes a layer of a printed circuit board (PCB), a pair of signal vias formed on the layer of the PCB and including a first signal via a second signal via each configured to propagate a respective signal, a first plurality of ground vias formed on the layer and at least partially circumferentially surrounding the first signal via of the pair of signal vias, and a second plurality of ground vias formed on the layer and at least partially circumferentially surrounding the second signal via of the pair of signal vias. The first plurality of ground vias and the second plurality of ground vias include a shared ground via.
    Type: Application
    Filed: December 7, 2023
    Publication date: April 24, 2025
    Inventors: Yuqing Zhu, Wenbin Ma, Mike Sapozhnikov, Weiying Ding, Mingjian Gao, Mingtong Zuo, David Nozadze, Joel Richard Goergen
  • Publication number: 20250063658
    Abstract: In some embodiments, an apparatus, includes a pad of a printed circuit board (PCB) configured to couple to an electrical component separate from the PCB and a via formed through the pad. The via is offset from a center of the pad such that a distance between the via and a most adjacent trace electrically separate from the via is above a threshold distance.
    Type: Application
    Filed: August 15, 2023
    Publication date: February 20, 2025
    Inventors: Mike Sapozhnikov, David Nozadze, Joel Richard Goergen, Wenbin Ma, Upen Reddy Kareti, Weiying Ding
  • Publication number: 20250031300
    Abstract: Provide for herein is an apparatus that includes multiple printed circuit board (PCB) layers and a via assembly. The via assembly includes a signal via extending through the multiple layers, and the signal via is configured to transmit a signal between the layers. The via assembly also includes a capacitive structure connected to the signal via to adjust an impedance of the via assembly along the via assembly. The capacitive structure is physically and electrically separate from other components of the PCB.
    Type: Application
    Filed: August 17, 2023
    Publication date: January 23, 2025
    Inventors: Mike Sapozhnikov, Amendra Koul, David Nozadze, Joel Richard Goergen, Upen Reddy Kareti, Sayed Ashraf Mamun
  • Publication number: 20250029931
    Abstract: In some embodiments, an integrated circuit (IC) includes multiple packages that are separate from one another. Each package includes a pad, and a core via is electrically coupled to the pads of the separate packages to electrically couple the packages to one another. At least one of the pads includes an oblong shape to match its impedance with the impedance of the core via.
    Type: Application
    Filed: August 22, 2023
    Publication date: January 23, 2025
    Inventors: Mike Sapozhnikov, Amendra Koul, David Nozadze, Joel Richard Goergen, Sayed Ashraf Mamun, Srinath Penugonda
  • Patent number: 12160948
    Abstract: A conductive signal transmission structure for a printed circuit includes a copper material and a graphene layer disposed within the copper material at a depth below a surface of the structure. The depth of the graphene layer is further within a skin depth region of the structure when a transmission signal applied to the conductive signal transmission structure has a signal speed of at least 112 Gbps and/or a Nyquist frequency that is at least about 14 gigahertz (GHz).
    Type: Grant
    Filed: June 20, 2023
    Date of Patent: December 3, 2024
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Joel Goergen, Scott Hinaga, Jessica Kiefer, Alpesh Umakant Bhobe, D. Brice Achkir, David Nozadze, Amendra Koul, Mehmet Onder Cap, Madeline Marie Roemer
  • Publication number: 20240355737
    Abstract: In some aspects, the techniques described herein relate to an apparatus including: a semiconductor device substrate material; a first signal conductor incorporated into the semiconductor device substrate material; a second signal conductor incorporated into the semiconductor device substrate material; and a ground conductor incorporated into the semiconductor device substrate material between the first signal conductor and the second signal conductor, wherein the ground conductor includes a first elongated portion and a second elongated portion arranged at an angle relative to the first elongated portion.
    Type: Application
    Filed: April 20, 2023
    Publication date: October 24, 2024
    Inventors: Wenbin Ma, Mike Sapozhnikov, Weiying Ding, David Nozadze, Yinxin Yang
  • Publication number: 20240356251
    Abstract: In some aspects, the techniques described herein relate to an apparatus for connecting cables to Input Output (IO) connector pins, including: a first Printed Circuit Board (PCB) configured to receive terminal ends of a plurality of cables, wherein the terminal ends of the plurality of cables are electrically isolated from one another in the first PCB; a second PCB configured to receive a plurality of IO connector pins, wherein the plurality of IO connector pins are electrically isolated from one another in the second PCB; and wherein the first PCB is configured to join to the second PCB to connect each of the terminal ends of the plurality of cables to corresponding pins of the plurality of IO connector pins.
    Type: Application
    Filed: August 25, 2023
    Publication date: October 24, 2024
    Inventors: David Nozadze, Mike Sapozhnikov, Amendra Koul, Sayed Ashraf Mamun, Upen Reddy Kareti
  • Publication number: 20240345180
    Abstract: Presented herein is a method comprising: determining skew values of cables, each skew value indicating a time of signal propagation along a respective cable at a respective signal frequency value, and the skew values being frequency dependent and varying at signal frequency values; determining skew behavior property values for each cable based on the skew values; determining a performance metric value for each skew behavior property value; determining a relationship between the skew values and the signal frequency values at each performance metric value based on the performance metric value for each skew behavior property value; and coupling a first electronic component and a second electronic component to one another using a new cable based on the relationship between the skew values and the signal frequency values at each performance metric value.
    Type: Application
    Filed: January 25, 2024
    Publication date: October 17, 2024
    Inventors: David Nozadze, Mike Sapozhnikov, Upen Reddy Kareti, Amendra Koul, Joel Richard Goergen
  • Patent number: 12003282
    Abstract: Channel predictive behavior and fault analysis may be provided. A forward time value may be determined comprising a time a forward signal takes to travel from a transmitter over a channel to the receiver. Next, a reflected time value may be determined comprising a time a reflected signal takes to travel to the receiver. The reflected signal may be associated with the forward signal. A discontinuity may then be determined to exist on the channel based on the forward time value and the reflected time value. The reflected signal may be caused by the discontinuity and a high impedance or low impedance at the transmitter present after the forward signal is sent.
    Type: Grant
    Filed: February 22, 2023
    Date of Patent: June 4, 2024
    Inventors: Amendra Koul, David Nozadze, Mike Sapozhnikov, Joel Goergen, Arnav Shailesh Shah
  • Patent number: 11894296
    Abstract: An apparatus includes an integrated circuit package and a heatsink. The integrated circuit package includes a substrate, an integrated circuit, a first plurality of signal conductors, and a second plurality of signal conductors. The substrate includes a first surface and a second surface opposite the first surface. The integrated circuit is coupled to the first surface of the substrate. The first plurality of signal conductors are arranged along a periphery of the first surface of the substrate. The second plurality of signal conductors are arranged along a periphery of the second surface of the substrate. The heatsink includes a first portion positioned along the first surface of the substrate and a second portion positioned along the second surface of the substrate.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: February 6, 2024
    Assignee: Cisco Technology, Inc.
    Inventors: Mike Sapozhnikov, Sayed Ashraf Mamun, Tomer Osi, Amendra Koul, David Nozadze, Upendranadh R. Kareti, Joel R. Goergen
  • Publication number: 20230397343
    Abstract: The techniques described herein relate to an apparatus including: a support structure of an integrated circuit device; and an elongated cavity formed in the support structure of the integrated circuit device, wherein an interior of the elongated cavity is plated with a conductive material separated into a first power connection portion and a first ground connection portion.
    Type: Application
    Filed: September 12, 2022
    Publication date: December 7, 2023
    Inventors: Mike Sapozhnikov, Sayed Ashraf Mamun, D. Brice Achkir, David Nozadze, Amendra Koul, Upen Reddy Kareti
  • Publication number: 20230354505
    Abstract: A conductive signal transmission structure for a printed circuit includes a copper material and a graphene layer disposed within the copper material at a depth below a surface of the structure. The depth of the graphene layer is further within a skin depth region of the structure when a transmission signal applied to the conductive signal transmission structure has a signal speed of at least 112 Gbps and/or a Nyquist frequency that is at least about 14 gigahertz (GHz).
    Type: Application
    Filed: June 20, 2023
    Publication date: November 2, 2023
    Inventors: Joel Goergen, Scott Hinaga, Jessica Kiefer, Alpesh Umakant Bhobe, D. Brice Achkir, David Nozadze, Amendra Koul, Mehmet Onder Cap, Madeline Marie Roemer
  • Patent number: 11777239
    Abstract: Certain aspects of the present disclosure provide techniques for pinless interconnect for twinaxial cables to an IC. This includes a socket coupled to an integrated circuit (IC), a port structure coupled to the socket, and a ground connector inserted into the port structure. It further includes a twinaxial cable including a pair of conductors inserted through the ground connector to establish an electrical connection between the twinaxial cable and the IC.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: October 3, 2023
    Assignee: Cisco Technology, Inc.
    Inventors: Mike Sapozhnikov, Sayed Ashraf Mamun, Tomer Osi, Amendra Koul, David Nozadze, Upendranadh R. Kareti, Joel R. Goergen