Abstract: Neutron detection cells and corresponding methods of detecting charged particles that make efficient use of silicon area are set forth. Three types of circuit cells/arrays are described: state latching circuits, glitch generating cells, and charge loss circuits. An array of these cells, used in conjunction with a neutron conversion film, increases the area that is sensitive to a strike by a charged particle over that of an array of SRAM cells. The result is a neutron detection cell that uses less power, costs less, and is more suitable for mass production.

Abstract: Neutron detection cells and corresponding methods of detecting charged particles that make efficient use of silicon area are set forth. Three types of circuit cells/arrays are described: state latching circuits, glitch generating cells, and charge loss circuits. An array of these cells, used in conjunction with a neutron conversion film, increases the area that is sensitive to a strike by a charged particle over that of an array of SRAM cells. The result is a neutron detection cell that uses less power, costs less, and is more suitable for mass production.

Abstract: A system and method for extending the operating life of a device susceptible to defects caused by total ionizing dose radiation and/or bias dependent degradation are described. The device is replicated at least once and at least one switching mechanism is used to cycle between the devices such that only one device is operating normally. While the first device is operating normally, the other devices are biased. The bias condition may slow, eliminate, or even reverse device shifts that occur due to total ionizing dose radiation or bias effects.

Abstract: A system and method for hardening dynamic logic against single event upset is described. A precharge circuit is hardened and then connected to two pull down networks. The two pull down networks are redundant and, under normal operating conditions, provide substantially the same outputs when receiving substantially the same inputs. The two outputs are then voted to provide an output that is hardened against single event upset. Alternatively, the two outputs may be connected to a next stage of dynamic logic circuits or other circuitry for evaluation.

Abstract: By adjusting a register's capturing clock edge timing so that the register captures data when the data returns to a correct state, the register may be protected against DSET upsets. If a data glitch occurs near the clock edge, the valid time at the register output is increased (CLK to Q). This valid time increase occurs when the presence of a DSET transient is detected near the clock edge.

Abstract: A voting scheme for analog signals is described. An analog block is replicated to provide three analog blocks that are designed to have substantially the same analog output based on receiving substantially the same input. Voting is used to compare the analog outputs from the three analog blocks. In one example, the analog output from one of the three analog blocks having a middle value between the values of the other two analog outputs is provided as an output of the voter circuit. In another example, if the original analog block provides the analog output having the middle value, the output of the original analog block is provided as an output of the voter circuit. Otherwise, an output of another analog block is provided as an output of the voter circuit. In another example, the analog voter circuit determines which of the three analog outputs have been impacted by a transient event based on a non-zero output of transconductor circuits.

Abstract: A system and method for extending the operating life of a device susceptible to defects caused by total ionizing dose radiation and/or bias dependent degradation are described. The device is replicated at least once and at least one switching mechanism is used to cycle between the devices such that only one device is operating normally. While the first device is operating normally, the other devices are biased. The bias condition may slow, eliminate, or even reverse device shifts that occur due to total ionizing dose radiation or bias effects.

Abstract: A system and method for providing error recovery to an asynchronous logic circuit is presented. The asynchronous logic circuit with error recovery may use temporal redundancy to compare the results of an asynchronous computation and initiate error recovery if necessary. Outputs of the asynchronous logic circuit are compared using a plurality of asynchronous register voters. If an asynchronous register voter detects an inconsistent result, the asynchronous register voter clears itself. A majority of common data outputs from the plurality of asynchronous register voters is provided as an output that is representative of the output of the asynchronous logic circuit.

Abstract: By adjusting a register's capturing clock edge timing so that the register captures data when the data returns to a correct state, the register may be protected against DSET upsets. If a data glitch occurs near the clock edge, the valid time at the register output is increased (CLK to Q). This valid time increase occurs when the presence of a DSET transient is detected near the clock edge.

Abstract: A system and method for hardening a Null Convention Logic (NCL) circuit against Single Event Upset (SEU) is presented. Placing a resistive element into a feedback loop of the NCL circuit may harden the NCL circuit. A bypass element may be placed in parallel with the resistive element to increase the latching speed of the hardened NCL circuit. Additionally, replacing transistors in an input driver, the feedback loop, and an inverter with transistor stacks, which may include two or more transistors connected in series, may harden the NCL circuit. Further, two NCL gates may be cross-coupled to harden the NCL circuit.

Abstract: A system and method for hardening a Null Convention Logic (NCL) circuit against Single Event Upset (SEU) is presented. Placing a resistive element into a feedback loop of the NCL circuit may harden the NCL circuit. A bypass element may be placed in parallel with the resistive element to increase the latching speed of the hardened NCL circuit. Additionally, replacing transistors in an input driver, the feedback loop, and an inverter with transistor stacks, which may include two or more transistors connected in series, may harden the NCL circuit. Further, two NCL gates may be cross-coupled to harden the NCL circuit.

Abstract: A radiation hardening circuit that includes two series-connected transistors that can replace any single transistor in a circuit. The hardening circuit includes a resistor that has a first node and a second node, a first transistor having a source terminal, a gate terminal, a drain terminal, and a body terminal. The first node of the resistor may be conductively connected to the drain terminal of the first transistor and the second node of the resistor is conductively connected to the body terminal of the first transistor. The hardening circuit also includes a second transistor in series with the first transistor, driven so that both transistors are off or on at any given time. The circuit is resistant to radiation-induced events due to the body bias of the first transistor, the off state of the second transistor, and the current limiting effect of the resistor.

Abstract: A system and method for hardening an asynchronous combinational logic circuit against Single Event Upset (SEU) is presented. The asynchronous combinational logic circuit is located between two asynchronous registers. A fault detector is used to detect a fault at an output of the asynchronous combinational logic circuit caused by SEU. If the fault detector detects a fault, a first asynchronous register is prevented from clearing stored data and a second asynchronous register is prevented from loading data from the asynchronous combinational logic circuit until the fault is cleared. Further, a timer circuit is used to ensure enough time elapses to allow the asynchronous combinational logic circuit to reevaluate itself. The asynchronous combinational logic circuit reevaluates itself by first propagating a NULL wave front to clear the fault and then propagating the data stored in the first asynchronous register to its outputs.

Abstract: A radiation hardening circuit that includes two series-connected transistors that can replace any single transistor in a circuit. The hardening circuit includes a resistor that has a first node and a second node, a first transistor having a source terminal, a gate terminal, a drain terminal, and a body terminal. The first node of the resistor may be conductively connected to the drain terminal of the first transistor and the second node of the resistor is conductively connected to the body terminal of the first transistor. The hardening circuit also includes a second transistor in series with the first transistor, driven so that both transistors are off or on at any given time. The circuit is resistant to radiation-induced events due to the body bias of the first transistor, the off state of the second transistor, and the current limiting effect of the resistor.