Patents by Inventor David O. Sullivan
David O. Sullivan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11941980Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for allowing vehicles access or egress from a dedicated roadway. In some implementations, a system includes a server, an interface, and sensors. The interface receives data from a railroad system that manages a railroad running parallel to a first roadway. The sensors are positioned in a location relative to the first and second roadway. Each sensor can detect vehicles on the second roadway. For each detected vehicle, each sensor can generate first sensor data based on the detected vehicle and the data received at the interface. Second sensor data can be generated based on activities on the first roadway. Observational data can be generated based on the first and second sensor data. An instruction can be determined to allow the detected vehicle access to the first roadway. The instruction can be transmitted to the detected vehicle.Type: GrantFiled: November 3, 2022Date of Patent: March 26, 2024Assignee: Cavnue Technology, LLCInventors: Mathew O'Sullivan, David Kiley
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Publication number: 20230343766Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a mold over and around a first die and a first via. The semiconductor package has a conductive pad of a first redistribution layer disposed on a top surface of the first die and/or a top surface of the mold. The semiconductor package includes a second die having a solder ball coupled to a die pad on a bottom surface of the second die, where the solder ball of the second die is coupled to the first redistribution layer. The first redistribution layer couples the second die to the first die, where the second die has a first edge and a second edge, and where the first edge is positioned within a footprint of the first die and the second edge is positioned outside the footprint of the first die.Type: ApplicationFiled: June 30, 2023Publication date: October 26, 2023Inventors: David O'SULLIVAN, Georg SEIDEMANN, Richard PATTEN, Bernd WAIDHAS
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Publication number: 20230317621Abstract: Embodiments herein relate to systems, apparatuses, techniques, or processes directed to semiconductor packages that include a glass interposer that includes electrically conductive through glass vias that extend through the interposer. One or more dies may be hybrid bonded to a first side of the glass interposer. In embodiments, the second side of the glass interposer may include a redistribution layer that is electrically coupled with the one or more dies through the through glass vias. Other embodiments may be described and/or claimed.Type: ApplicationFiled: March 29, 2022Publication date: October 5, 2023Inventors: Bernd WAIDHAS, David O'SULLIVAN, Georg SEIDEMANN
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Patent number: 11735570Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a mold over and around a first die and a first via. The semiconductor package has a conductive pad of a first redistribution layer disposed on a top surface of the first die and/or a top surface of the mold. The semiconductor package includes a second die having a solder ball coupled to a die pad on a bottom surface of the second die, where the solder ball of the second die is coupled to the first redistribution layer. The first redistribution layer couples the second die to the first die, where the second die has a first edge and a second edge, and where the first edge is positioned within a footprint of the first die and the second edge is positioned outside the footprint of the first die.Type: GrantFiled: April 4, 2018Date of Patent: August 22, 2023Assignee: Intel CorporationInventors: David O'Sullivan, Georg Seidemann, Richard Patten, Bernd Waidhas
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Publication number: 20220310777Abstract: IC chip package routing structures including a metal-insulator-metal (MIM) capacitor integrated with redistribution layers. An active side of an IC chip may be electrically coupled to the redistribution layers through first-level interconnects. The redistribution layers terminate at interfaces suitable for coupling a package to a host component through second-level interconnects. The MIM capacitor structure may comprise materials suitable for high temperature processing, for example of 350° C., or more. The MIM capacitor structure may therefore be fabricated over a host substrate using higher temperature processing. The redistribution layers and MIM capacitor may then be embedded within package dielectric material(s) using lower temperature processing. An IC chip may be attached to the package routing structure, and the package then separated from the host substrate for further assembly to a host component.Type: ApplicationFiled: March 26, 2021Publication date: September 29, 2022Applicant: Intel CorporationInventors: David O'Sullivan, Georg Seidemann, Bernd Waidhas, Horst Baumeister
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Patent number: 11380616Abstract: Fan Out Package-On-Package (PoP) assemblies in which a second chip is adhered to a non-active side of a first chip. An active side of the first chip embedded in a first package material may be electrically coupled through one or more redistribution layers that fan out to package interconnects on a first side of the POP. A second chip may be adhered, with a second package material, to the non-active side of the first chip. An active side of the second chip may be electrically coupled to the package interconnects through a via structure extending through the first package material. Second interconnects between the second chip, or a package thereof, may contact the via structure. Use of the second package material as an adhesive may improve positional stability of the second chip to facilitate wafer-level assembly techniques.Type: GrantFiled: May 16, 2018Date of Patent: July 5, 2022Assignee: Intel IP CorporationInventors: David O'Sullivan, Bernd Waidhas, Thomas Huber
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Patent number: 10602679Abstract: A harvesting tumbler apparatus includes first and second spaced apart grating segment retainers, and a tumbler grating including a plurality of resiliently tensionable grating segments connected to the first and second grating segment retainers. The resiliently tensionable grating segments extend from each of the first and second grating segment retainers in a spaced apart circular arrangement. The tumbler apparatus further includes a tension mechanism configured to apply a sufficient tension force to the resiliently tensionable grating segments to cause the grating to form a cylindrical shape. In illustrative embodiments, the resiliently tensionable grating segments may include flexible cord segments.Type: GrantFiled: March 31, 2017Date of Patent: March 31, 2020Assignee: Eteros Technologies Inc.Inventors: Aaron McKellar, Amanda McKellar, Erik Ingram, Rudi Klossok, Joe Heywood, David O'Sullivan
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Publication number: 20200098698Abstract: Embodiments include semiconductor packages, such as wafer level chip scale packages (WLCSPs), flip chip chip scale packages (FCCSPs), and fan out packages. The WLCSP includes a first doped region on a second doped region, a dielectric on a redistribution layer, where the dielectric is between the redistribution layer and doped regions. The WLCSP also includes a shield over the doped regions, the dielectric, and the redistribution layer, where the shield includes a plurality of surfaces, and at least one of the plurality of surfaces of the shield is on a top surface of the first doped region. The WLCSP may have interconnects coupled to the second doped region and redistribution layer. The shield may be a conductive shield that is coupled to ground, and the shield may be directly coupled to the redistribution layer and first doped region. The first and second doped regions may include highly doped n-type materials.Type: ApplicationFiled: September 26, 2018Publication date: March 26, 2020Inventors: Richard PATTEN, David O'SULLIVAN, Georg SEIDEMANN, Bernd WAIDHAS
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Publication number: 20190355659Abstract: Fan Out Package-On-Package (PoP) assemblies in which a second chip is adhered to a non-active side of a first chip. An active side of the first chip embedded in a first package material may be electrically coupled through one or more redistribution layers that fan out to package interconnects on a first side of the POP. A second chip may be adhered, with a second package material, to the non-active side of the first chip. An active side of the second chip may be electrically coupled to the package interconnects through a via structure extending through the first package material. Second interconnects between the second chip, or a package thereof, may contact the via structure. Use of the second package material as an adhesive may improve positional stability of the second chip to facilitate wafer-level assembly techniques.Type: ApplicationFiled: May 16, 2018Publication date: November 21, 2019Applicant: Intel IP CorporationInventors: David O'Sullivan, Bernd Waidhas, Thomas Huber
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Publication number: 20190312016Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a mold over and around a first die and a first via. The semiconductor package has a conductive pad of a first redistribution layer disposed on a top surface of the first die and/or a top surface of the mold. The semiconductor package includes a second die having a solder ball coupled to a die pad on a bottom surface of the second die, where the solder ball of the second die is coupled to the first redistribution layer. The first redistribution layer couples the second die to the first die, where the second die has a first edge and a second edge, and where the first edge is positioned within a footprint of the first die and the second edge is positioned outside the footprint of the first die.Type: ApplicationFiled: April 4, 2018Publication date: October 10, 2019Inventors: David O'Sullivan, Georg Seidemann, Richard Patten, Bernd Waidhas
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Publication number: 20180279564Abstract: A harvesting tumbler apparatus includes first and second spaced apart grating segment retainers, and a tumbler grating including a plurality of resiliently tensionable grating segments connected to the first and second grating segment retainers. The resiliently tensionable grating segments extend from each of the first and second grating segment retainers in a spaced apart circular arrangement. The tumbler apparatus further includes a tension mechanism configured to apply a sufficient tension force to the resiliently tensionable grating segments to cause the grating to form a cylindrical shape. In illustrative embodiments, the resiliently tensionable grating segments may include flexible cord segments.Type: ApplicationFiled: March 31, 2017Publication date: October 4, 2018Applicant: ETEROS TECHNOLOGIES INC.Inventors: Aaron McKellar, Amanda McKellar, Erik Ingram, Rudi Klossok, Joe Heywood, David O'Sullivan
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Publication number: 20180064712Abstract: The present invention encompasses methods of reducing inflammatory immune cell activation and inflammation via inhibiting mitochondrial fission.Type: ApplicationFiled: June 8, 2017Publication date: March 8, 2018Applicant: Max Planck InstituteInventors: Erika L. Pearce, Michael D. Buck, David O'Sullivan, Francesc Baixauli
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Patent number: 9646856Abstract: A method of manufacturing a device includes providing a semiconductor chip having a first face and a second face opposite to the first face with a contact pad arranged on the first face. The semiconductor chip is placed on a carrier with the first face facing the carrier. The semiconductor chip is encapsulated with an encapsulation material. The carrier is removed and the semiconductor material is removed from the second face of the first semiconductor chip without removing encapsulation material at the same time.Type: GrantFiled: May 19, 2015Date of Patent: May 9, 2017Assignee: Intel Deutschland GmbHInventors: Thorsten Meyer, Klaus Reingruber, David O'Sullivan
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Publication number: 20170101624Abstract: The present disclosure encompasses methods of enhancing T cell longevity and/or T cell function by promoting mitochondrial fusion and/or mitochondrial structural remodeling including cristae. Compositions comprising the enhanced T cells may be used in adoptive cellular immunotherapy.Type: ApplicationFiled: October 6, 2016Publication date: April 13, 2017Inventors: Erika L. Pearce, Michael D. Buck, David O'Sullivan
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Patent number: 9473729Abstract: Display features of an interactive user interface for a TV environment allow a user to interact with objects and/or information within a display space.Type: GrantFiled: October 17, 2008Date of Patent: October 18, 2016Assignee: Sky UK LimitedInventors: Marisa Miles, Gerry David O'Sullivan, Robin Crossley, Nicholas James
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Publication number: 20150262844Abstract: A method of manufacturing a device includes providing a semiconductor chip having a first face and a second face opposite to the first face with a contact pad arranged on the first face. The semiconductor chip is placed on a carrier with the first face facing the carrier. The semiconductor chip is encapsulated with an encapsulation material. The carrier is removed and the semiconductor material is removed from the second face of the first semiconductor chip without removing encapsulation material at the same time.Type: ApplicationFiled: May 19, 2015Publication date: September 17, 2015Inventors: Thorsten Meyer, Klaus Reingruber, David O'Sullivan
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Patent number: 9111947Abstract: A chip arrangement may include: a semiconductor chip; an encapsulating structure at least partially encapsulating the semiconductor chip, the encapsulating structure having a first side and a second side opposite the first side, the encapsulating structure including a recess over the first side of the encapsulating structure, the recess having a bottom surface located at a first level; and at least one electrical connector disposed at the first side of the encapsulating structure outside the recess, wherein a surface of the at least one electrical connector facing the encapsulating structure may be disposed at a second level different from the first level.Type: GrantFiled: June 4, 2013Date of Patent: August 18, 2015Assignee: INTEL DEUTSCHLAND GMBHInventors: David O'Sullivan, Thorsten Meyer
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Patent number: 9064883Abstract: A method of manufacturing a device includes providing a semiconductor chip having a first face and a second face opposite to the first face with a contact pad arranged on the first face. The semiconductor chip is placed on a carrier with the first face facing the carrier. The semiconductor chip is encapsulated with an encapsulation material. The carrier is removed and the semiconductor material is removed from the second face of the first semiconductor chip without removing encapsulation material at the same time.Type: GrantFiled: August 25, 2011Date of Patent: June 23, 2015Assignee: Intel Mobile Communications GmbHInventors: Thorsten Meyer, Klaus Reingruber, David O'Sullivan
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Publication number: 20140353836Abstract: A chip arrangement may include: a semiconductor chip; an encapsulating structure at least partially encapsulating the semiconductor chip, the encapsulating structure having a first side and a second side opposite the first side, the encapsulating structure including a recess over the first side of the encapsulating structure, the recess having a bottom surface located at a first level; and at least one electrical connector disposed at the first side of the encapsulating structure outside the recess, wherein a surface of the at least one electrical connector facing the encapsulating structure may be disposed at a second level different from the first level.Type: ApplicationFiled: June 4, 2013Publication date: December 4, 2014Inventors: David O'Sullivan, Thorsten Meyer
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Publication number: 20140328879Abstract: Probiotic Bifidobacterium strain AH1205 or mutants or variants thereof are immunomodulatory following oral consumption and are useful in the prophylaxis and/or treatment of inflammatory activity such as undesirable gastrointestinal inflammatory activity for example inflammatory bowel disease.Type: ApplicationFiled: March 18, 2014Publication date: November 6, 2014Applicant: ALIMENTARY HEALTH LIMITEDInventors: John MacSharry, Liam O'Mahony, David O'Sullivan, Barry Kiely