Patents by Inventor David Ofelt

David Ofelt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10547333
    Abstract: In some embodiments, an apparatus includes an optical transceiver which includes a rate-adaptive forward error correction (FEC) encoder and a rate-adaptive FEC decoder. The rate-adaptive FEC encoder is configured to adjust a number of a set of known symbols associated with a codeword to achieve rate adaption. A length of the codeword is fixed. The rate-adaptive FEC encoder is configured to generate the codeword based on (1) a set of information symbols including the set of known symbols and a set of data symbols, and (2) a fixed number of a set of parity symbols generated using information symbols. The rate-adaptive FEC decoder is configured to receive a set of reliability values associated with a channel word, and expand the set of reliability values to produce an expanded set of reliability values. The rate-adaptive FEC decoder is further configured to decode the expanded set of reliability values.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: January 28, 2020
    Assignee: Juniper Networks, Inc.
    Inventors: Murat Arabaci, Marianna Pepe, Philip A. Thomas, David Ofelt, Massimiliano Salsi
  • Patent number: 9906243
    Abstract: In some embodiments, an apparatus includes an optical transceiver which includes a rate-adaptive forward error correction (FEC) encoder and a rate-adaptive FEC decoder. The rate-adaptive FEC encoder is configured to adjust a number of a set of known symbols associated with a codeword to achieve rate adaption. A length of the codeword is fixed. The rate-adaptive FEC encoder is configured to generate the codeword based on (1) a set of information symbols including the set of known symbols and a set of data symbols, and (2) a fixed number of a set of parity symbols generated using information symbols. The rate-adaptive FEC decoder is configured to receive a set of reliability values associated with a channel word, and expand the set of reliability values to produce an expanded set of reliability values. The rate-adaptive FEC decoder is further configured to decode the expanded set of reliability values.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: February 27, 2018
    Assignee: Juniper Networks, Inc.
    Inventors: Murat Arabaci, Marianna Pepe, Philip A. Thomas, David Ofelt, Massimiliano Salsi
  • Patent number: 8483222
    Abstract: The invention is directed to techniques for supporting multi-link protocols within a computer network. In one embodiment, a method includes receiving a set of data blocks from a plurality of links in one or more interface cards according to a multi-link protocol and sending the data blocks to a multi-link service card for sequencing. The data blocks may then be sent to the one or more interface cards for communication to a destination device over a computer network. Implementing a multi-link service card may allow a network device, such as a router, to support multi-link protocols.
    Type: Grant
    Filed: November 8, 2007
    Date of Patent: July 9, 2013
    Assignee: Juniper Networks, Inc.
    Inventors: David Ofelt, Steven Wilson Turner, Dennis Ferguson
  • Publication number: 20110072301
    Abstract: A system includes a group of devices and a shared memory that is partitioned into blocks that are capable of being allocated to the group of devices using linked lists. The system also includes check logic configured to store a group of bits, where each bit corresponds to one of the blocks, and counter logic configured to count for a predetermined period of time. The system further includes logic configured to clear the group of bits stored in the check logic, cause the counter logic to count for the predetermined period of time, monitor a de-allocation of the blocks in the shared memory, set, for each of the blocks that is de-allocated during the predetermined period of time, the corresponding bit in the check logic, identify, after the predetermined period of time, one or more bits that have not been set, and mark the blocks corresponding to the one or more bits as available for allocation.
    Type: Application
    Filed: November 30, 2010
    Publication date: March 24, 2011
    Applicant: JUNIPER NETWORKS, INC.
    Inventors: Debashis BASU, David OFELT
  • Patent number: 7870421
    Abstract: A system includes a group of devices and a shared memory that is partitioned into blocks that are capable of being allocated to the group of devices using linked lists. The system also includes check logic configured to store a group of bits, where each bit corresponds to one of the blocks, and counter logic configured to count for a predetermined period of time. The system further includes logic configured to clear the group of bits stored in the check logic, cause the counter logic to count for the predetermined period of time, monitor a de-allocation of the blocks in the shared memory, set, for each of the blocks that is de-allocated during the predetermined period of time, the corresponding bit in the check logic, identify, after the predetermined period of time, one or more bits that have not been set, and mark the blocks corresponding to the one or more bits as available for allocation.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: January 11, 2011
    Assignee: Juniper Networks, Inc.
    Inventors: Debashis Basu, David Ofelt
  • Publication number: 20080133965
    Abstract: A system includes a group of devices and a shared memory that is partitioned into blocks that are capable of being allocated to the group of devices using linked lists. The system also includes check logic configured to store a group of bits, where each bit corresponds to one of the blocks, and counter logic configured to count for a predetermined period of time. The system further includes logic configured to clear the group of bits stored in the check logic, cause the counter logic to count for the predetermined period of time, monitor a de-allocation of the blocks in the shared memory, set, for each of the blocks that is de-allocated during the predetermined period of time, the corresponding bit in the check logic, identify, after the predetermined period of time, one or more bits that have not been set, and mark the blocks corresponding to the one or more bits as available for allocation.
    Type: Application
    Filed: January 16, 2008
    Publication date: June 5, 2008
    Applicant: JUNIPER NETWORKS, INC.
    Inventors: Debashis BASU, David OFELT
  • Patent number: 7343513
    Abstract: A system includes a group of devices and a shared memory that is partitioned into blocks that are capable of being allocated to the group of devices using linked lists. The system also includes check logic configured to store a group of bits, where each bit corresponds to one of the blocks, and counter logic configured to count for a predetermined period of time. The system further includes logic configured to clear the group of bits stored in the check logic, cause the counter logic to count for the predetermined period of time, monitor a de-allocation of the blocks in the shared memory, set, for each of the blocks that is de-allocated during the predetermined period of time, the corresponding bit in the check logic, identify, after the predetermined period of time, one or more bits that have not been set, and mark the blocks corresponding to the one or more bits as available for allocation.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: March 11, 2008
    Assignee: Juniper Networks, Inc.
    Inventors: Debashis Basu, David Ofelt
  • Patent number: 7315900
    Abstract: The invention is directed to techniques for supporting multi-link protocols within a computer network. In one embodiment, a method includes receiving a set of data blocks from a plurality of links in one or more interface cards according to a multi-link protocol and sending the data blocks to a multi-link service card for sequencing. The data blocks may then be sent to the one or more interface cards for communication to a destination device over a computer network. Implementing a multi-link service card may allow a network device, such as a router, to support multi-link protocols.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: January 1, 2008
    Assignee: Juniper Networks, Inc.
    Inventors: David Ofelt, Steven Wilson Turner, Dennis Ferguson