Abstract: Systems, methods and apparatus are provided for a multi-coil induction apparatus. The multi-coil induction apparatus has a primary coil structure with a primary first coil portion and a primary second coil portion where both are on a common planar surface; and a secondary coil structure having a secondary first coil portion and a secondary second coil, where the secondary first coil portion and the secondary second coil portion are coplanar with the primary first coil portion and the primary second coil. The primary first coil portion and the secondary first coil portion concentrically turn on the common planar surface to form a coupled induction section while the primary second coil portion and the secondary second coil portion are adjacent the coupled induction section on the common planar surface.

Abstract: A memory module is coupled to a number of controllers. The memory module is configured to configure each of a number of data input/output ports thereof as at least one of an input and an output in response to a first command from a particular controller of the controllers. The memory module is configured to partition itself into memory partitions in response to a second command from the particular controller so that each memory partition corresponds to a respective one of the controllers. Each of a number of data input/output ports of the controllers is configurable as at least one of an input and an output to correspond to a respective one of the input/output ports of the memory module. The first and second commands may originate from the particular controller, or the controllers may be coupled in parallel to the memory module.

Abstract: A memory module is coupled to a number of controllers. The memory module is configured to configure each of a number of data input/output ports thereof as at least one of an input and an output in response to a first command from a particular controller of the controllers. The memory module is configured to partition itself into memory partitions in response to a second command from the particular controller so that each memory partition corresponds to a respective one of the controllers. Each of a number of data input/output ports of the controllers is configurable as at least one of an input and an output to correspond to a respective one of the input/output ports of the memory module. The first and second commands may originate from the particular controller, or the controllers may be coupled in parallel to the memory module.

Abstract: A memory module has one or more memory devices, a controller in communication with the one or more memory devices, and a plurality of input/output ports. The controller is configured to configure each input/output port as an input, an output, or a bidirectional input/output.

Abstract: A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.

Abstract: A memory module has one or more memory devices, a controller in communication with the one or more memory devices, and a plurality of input/output ports. The controller is configured to configure each input/output port as an input, an output, or a bidirectional input/output.

Abstract: A method and system for generating a reference voltage for memory device signal receivers operates in either a calibration mode or a normal operating mode. In the calibration mode, the magnitude of the reference voltage is incrementally varied, and a digital signal pattern is coupled to the receiver at each reference voltage. An output of the receiver is analyzed to determine if the receiver can accurately pass the signal pattern at each reference voltage level. A range of reference voltages that allow the receiver to accurately pass the signal pattern is recorded, and a final reference voltage is calculated at the approximate midpoint of the range. This final reference voltage is applied to the receiver during normal operation.

Abstract: A system for de-emphasizing digital signals, such as address signals, boosts the level of the signals for one clock period prior to transmitting the signals through signal lines that may have a relatively large capacitance. The system may include a delay circuit that delays the digital signal for a period corresponding to one period of a clock signal. The system may also include a first multiplier circuit that generates a first intermediate signal by multiplying the first and second logic levels of the digital signal by a first multiplier. Similarly, a second multiplier circuit generates a second intermediate signal by multiplying the first and second logic levels of the delayed signal from the delay circuit by a second multiplier. A combining circuit then subtracts the second intermediate signal from the first intermediate signal, and the resulting signal is level-adjusted to generate the de-emphasized signal.

Abstract: A system for de-emphasizing digital signals, such as address signals, boosts the level of the signals for one clock period prior to transmitting the signals through signal lines that may have a relatively large capacitance. The system may include a delay circuit that delays the digital signal for a period corresponding to one period of a clock signal. The system may also include a first multiplier circuit that generates a first intermediate signal by multiplying the first and second logic levels of the digital signal by a first multiplier. Similarly, a second multiplier circuit generates a second intermediate signal by multiplying the first and second logic levels of the delayed signal from the delay circuit by a second multiplier. A combining circuit then subtracts the second intermediate signal from the first intermediate signal, and the resulting signal is level-adjusted to generate the de-emphasized signal.

Abstract: A method and system for coupling digital signals from a first location to a second location through respective signal lines includes a mode detector that detects each of the transitions of the digital signals. The mode detector determines respective propagation times of the signals through the signal lines based on the relative transitions of the signals. The mode detector then applies delay values to delay circuits that couple the signals to the signal lines with respective delays corresponding to the delay values. The delay values may be determined by coupling a predetermined pattern of test signals through the signal lines and determining which delay values allow the signals to be most accurately captured at the second location.

Abstract: A system for de-emphasizing digital signals, such as address signals, boosts the level of the signals for one clock period prior to transmitting the signals through signal lines that may have a relatively large capacitance. The system may include a delay circuit that delays the digital signal for a period corresponding to one period of a clock signal. The system may also include a first multiplier circuit that generates a first intermediate signal by multiplying the first and second logic levels of the digital signal by a first multiplier. Similarly, a second multiplier circuit generates a second intermediate signal by multiplying the first and second logic levels of the delayed signal from the delay circuit by a second multiplier. A combining circuit then subtracts the second intermediate signal from the first intermediate signal, and the resulting signal is level-adjusted to generate the de-emphasized signal.

Abstract: A system for de-emphasizing digital signals, such as address signals, boosts the level of the signals for one clock period prior to transmitting the signals through signal lines that may have a relatively large capacitance. The system may include a delay circuit that delays the digital signal for a period corresponding to one period of a clock signal. The system may also include a first multiplier circuit that generates a first intermediate signal by multiplying the first and second logic levels of the digital signal by a first multiplier. Similarly, a second multiplier circuit generates a second intermediate signal by multiplying the first and second logic levels of the delayed signal from the delay circuit by a second multiplier. A combining circuit then subtracts the second intermediate signal from the first intermediate signal, and the resulting signal is level-adjusted to generate the de-emphasized signal.

Abstract: A radio frequency identification device includes an integrated circuit including a receiver, a transmitter, and a microprocessor. The receiver and transmitter together define an active transponder. The integrated circuit is preferably a monolithic single die integrated circuit including the receiver, the transmitter, and the microprocessor. Because the device includes an active transponder, instead of a transponder which relies on magnetic coupling for power, the device has a much greater range.

Abstract: A radio frequency identification device includes an integrated circuit including a receiver, a transmitter, and a microprocessor. The receiver and transmitter together define an active transponder. The integrated circuit is preferably a monolithic single die integrated circuit including the receiver, the transmitter, and the microprocessor. Because the device includes an active transponder, instead of a transponder which relies on magnetic coupling for power, the device has a much greater range.

Abstract: A radio frequency identification device includes an integrated circuit including a receiver, a transmitter, and a microprocessor. The receiver and transmitter together define an active transponder. The integrated circuit is preferably a monolithic single die integrated circuit including the receiver, the transmitter, and the microprocessor. Because the device includes an active transponder, instead of a transponder which relies on magnetic coupling for power, the device has a much greater range.

Abstract: A radio frequency identification device includes an integrated circuit including a receiver, a transmitter, and a microprocessor. The receiver and transmitter together define an active transponder. The integrated circuit is preferably a monolithic single die integrated circuit including the receiver, the transmitter, and the microprocessor. Because the device includes an active transponder, instead of a transponder which relies on magnetic coupling for power, the device has a much greater range.

Abstract: The present invention relates to wireless communication systems, interrogators and methods of communicating within a wireless communication system. One aspect of the present invention provides a wireless communication system including at least one remote communication device configured to communicate a return link wireless signal; an interrogator including: a communication station configured to receive the return link wireless signal and to generate a return link communication signal corresponding to the return link wireless signal; communication circuitry coupled with the communication station and configured to communicate the return link communication signal; and a housing remotely located with respect to the communication station and including circuitry configured to receive the return link communication signal from the communication circuitry and to process the return link communication signal.

Abstract: The present invention includes phase shifters, interrogators, methods of shifting a phase angle of a signal, and methods of operating an interrogator. One aspect of the present invention provides a phase shifter including a first power divider configured to receive a signal and provide plural quadrature components of the signal; plural mixers coupled with the first power divider and configured to scale the quadrature components using a phase shift angle; and a second power divider coupled with the mixers and configured to combine the scaled quadrature components to shift the phase angle of the input signal by the phase shift angle.

Abstract: The present invention provides backscatter interrogators, communication systems and backscatter communication methods. According to one aspect of the present invention, a backscatter interrogator includes a data path configured to communicate a data signal; a signal generator configured to generate a carrier signal; and a modulator coupled with the data path and the signal generator, the modulator being configured to spread the data signal to define a spread data signal and amplitude modulate the carrier signal using the spread data signal, the modulator being further configured to phase modulate the carrier signal.

Abstract: A radio frequency identification device includes an integrated circuit including a receiver, a transmitter, and a microprocessor. The receiver and transmitter together define an active transponder. The integrated circuit is preferably a monolithic single die integrated circuit including the receiver, the transmitter, and the microprocessor. Because the device includes an active transponder, instead of a transponder which relies on magnetic coupling for power, the device has a much greater range.