Patents by Inventor David P. Brunco
David P. Brunco has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10811422Abstract: Methods according to the disclosure include forming a mask over a substrate to cover a first semiconductor region on the substrate and a first gate structure on the first semiconductor region. The second semiconductor region may be recessed from an initial height above the substrate to a reduced height above the substrate. The mask may be removed before forming a plurality of cavities by etching the first and second semiconductor regions, the plurality of cavities including a first cavity having a first depth within the first semiconductor region and a second cavity having a second depth within the second semiconductor region, wherein the second depth is greater than the first depth. The method also may include forming a plurality of epitaxial regions within the plurality of cavities.Type: GrantFiled: November 20, 2018Date of Patent: October 20, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Yanping Shen, Wei Hong, Hui Zang, David P. Brunco
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Patent number: 10727067Abstract: Methods of forming a structure that includes a field-effect transistor and structures that include a field effect-transistor. A cut is formed that extends through a gate structure of the field-effect transistor such that a gate electrode of the gate structure is divided into a first section having a first surface and a second section having a second surface spaced across the cut from the first surface. After forming the cut, a first section of a conductive layer is selectively deposited on the first surface of the first section of the gate electrode and a second section of the conductive layer is selectively deposited on the second surface of the second section of the gate electrode to shorten the cut. A dielectric material is deposited in the cut between the first and second sections of the conductive layer on the first and second surfaces of the gate electrode to form a dielectric pillar.Type: GrantFiled: November 29, 2018Date of Patent: July 28, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Hui Zang, David P. Brunco
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Publication number: 20200176258Abstract: Methods of forming a structure that includes a field-effect transistor and structures that include a field effect-transistor. A cut is formed that extends through a gate structure of the field-effect transistor such that a gate electrode of the gate structure is divided into a first section having a first surface and a second section having a second surface spaced across the cut from the first surface. After forming the cut, a first section of a conductive layer is selectively deposited on the first surface of the first section of the gate electrode and a second section of the conductive layer is selectively deposited on the second surface of the second section of the gate electrode to shorten the cut. A dielectric material is deposited in the cut between the first and second sections of the conductive layer on the first and second surfaces of the gate electrode to form a dielectric pillar.Type: ApplicationFiled: November 29, 2018Publication date: June 4, 2020Inventors: Hui Zang, David P. Brunco
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Publication number: 20200161315Abstract: Methods according to the disclosure include forming a mask over a substrate to cover a first semiconductor region on the substrate and a first gate structure on the first semiconductor region. The second semiconductor region may be recessed from an initial height above the substrate to a reduced height above the substrate. The mask may be removed before forming a plurality of cavities by etching the first and second semiconductor regions, the plurality of cavities including a first cavity having a first depth within the first semiconductor region and a second cavity having a second depth within the second semiconductor region, wherein the second depth is greater than the first depth. The method also may include forming a plurality of epitaxial regions within the plurality of cavities.Type: ApplicationFiled: November 20, 2018Publication date: May 21, 2020Inventors: Yanping Shen, Wei Hong, Hui Zang, David P. Brunco
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Publication number: 20190273148Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.Type: ApplicationFiled: May 17, 2019Publication date: September 5, 2019Inventors: Wei Zhao, Haiting Wang, David P. Brunco, Jiehui Shu, Shesh Mani Pandey, Jinping Liu, Scott Beasor
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Patent number: 10403742Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.Type: GrantFiled: September 22, 2017Date of Patent: September 3, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Wei Zhao, Haiting Wang, David P. Brunco, Jiehui Shu, Shesh Mani Pandey, Jinping Liu, Scott Beasor
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Patent number: 10325811Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. A plurality of sacrificial layers are formed on a dielectric layer. An opening is formed that includes a first section that extends through the sacrificial layers and a second section that extends through the dielectric layer. A semiconductor material is epitaxially grown inside the opening to form a fin. The first section of the opening has a first width dimension, and the second section of the opening has a second width dimension that is less than the first width dimension.Type: GrantFiled: October 26, 2017Date of Patent: June 18, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: David P. Brunco, Wei Zhao, Haiting Wang
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Publication number: 20190131177Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. A plurality of sacrificial layers are formed on a dielectric layer. An opening is formed that includes a first section that extends through the sacrificial layers and a second section that extends through the dielectric layer. A semiconductor material is epitaxially grown inside the opening to form a fin. The first section of the opening has a first width dimension, and the second section of the opening has a second width dimension that is less than the first width dimension.Type: ApplicationFiled: October 26, 2017Publication date: May 2, 2019Inventors: David P. Brunco, Wei Zhao, Haiting Wang
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Publication number: 20190097019Abstract: Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.Type: ApplicationFiled: September 22, 2017Publication date: March 28, 2019Inventors: Wei Zhao, Haiting Wang, David P. Brunco, Jiehui Shu, Shesh Mani Pandey, Jinping Liu, Scott Beasor
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Patent number: 10002793Abstract: A gap fill method for sub-fin doping includes forming semiconductor fin arrays over a semiconductor substrate, forming a first dopant source layer over a first fin array and filling intra fin gaps within the first array, and forming a second dopant source layer over a second fin array and filling intra fin gaps within the second array. The first and second dopant source layers are recessed to expose a channel region of the fins. Thereafter, an annealing step is used to drive dopants from the dopant source layers locally into sub-fin regions of the fins below the channel regions.Type: GrantFiled: March 21, 2017Date of Patent: June 19, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Jiehui Shu, David P. Brunco, Jinping Liu, Baofu Zhu, Shesh Mani Pandey
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Patent number: 9953872Abstract: Embodiments of the present invention provide a semiconductor structure having a strain relaxed buffer, and method of fabrication. A strain relaxed buffer is disposed on a semiconductor substrate. A silicon region and silicon germanium region are disposed adjacent to each other on the strain relaxed buffer. An additional region of silicon or silicon germanium provides quantum well isolation.Type: GrantFiled: September 8, 2017Date of Patent: April 24, 2018Assignee: GLOBALFOUNDRIES INC.Inventor: David P. Brunco
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Publication number: 20180012805Abstract: Embodiments of the present invention provide a semiconductor structure having a strain relaxed buffer, and method of fabrication. A strain relaxed buffer is disposed on a semiconductor substrate. A silicon region and silicon germanium region are disposed adjacent to each other on the strain relaxed buffer. An additional region of silicon or silicon germanium provides quantum well isolation.Type: ApplicationFiled: September 8, 2017Publication date: January 11, 2018Applicant: GLOBALFOUDRIES INC.Inventor: David P. Brunco
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Patent number: 9793168Abstract: Embodiments of the present invention provide a semiconductor structure having a strain relaxed buffer, and method of fabrication. A strain relaxed buffer is disposed on a semiconductor substrate. A silicon region and silicon germanium region are disposed adjacent to each other on the strain relaxed buffer. An additional region of silicon or silicon germanium provides quantum well isolation.Type: GrantFiled: December 21, 2015Date of Patent: October 17, 2017Assignee: GLOBALFOUNDRIES INC.Inventor: David P. Brunco
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Publication number: 20160111335Abstract: Embodiments of the present invention provide a semiconductor structure having a strain relaxed buffer, and method of fabrication. A strain relaxed buffer is disposed on a semiconductor substrate. A silicon region and silicon germanium region are disposed adjacent to each other on the strain relaxed buffer. An additional region of silicon or silicon germanium provides quantum well isolation.Type: ApplicationFiled: December 21, 2015Publication date: April 21, 2016Inventor: David P. Brunco
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Patent number: 9299809Abstract: One illustrative method disclosed herein includes forming a silicon/germanium fin in a layer of insulating material, wherein the fin has a first germanium concentration, recessing an upper surface of the layer of insulating material so as to expose a portion of the fin, performing an oxidation process so as to oxidize at least a portion of the fin and form a region in the exposed portion of the fin that has a second germanium concentration that is greater than the first germanium concentration, removing the oxide materials from the fin that was formed during the oxidation process and forming a gate structure that is positioned around at least the region having the second germanium concentration.Type: GrantFiled: December 17, 2012Date of Patent: March 29, 2016Assignee: GLOBALFOUNDRIES Inc.Inventor: David P. Brunco
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Patent number: 9257557Abstract: Embodiments of the present invention provide a semiconductor structure having a strain relaxed buffer, and method of fabrication. A strain relaxed buffer is disposed on a semiconductor substrate. A silicon region and silicon germanium region are disposed adjacent to each other on the strain relaxed buffer. An additional region of silicon or silicon germanium provides quantum well isolation.Type: GrantFiled: May 20, 2014Date of Patent: February 9, 2016Assignee: GLOBALFOUNDRIES INC.Inventor: David P. Brunco
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Publication number: 20160035727Abstract: A CMOS structure with beneficial nMOS and pMOS band offsets is disclosed. A first silicon germanium layer is formed on a semiconductor substrate. A second silicon germanium layer is formed on the first silicon germanium layer. The second silicon germanium layer has a higher germanium percentage than the first silicon germanium layer. Furthermore, the germanium concentration of the two layers is selected such that there is a beneficial band offset for both N-type field effect transistors and P-type field effect transistors in a CMOS structure.Type: ApplicationFiled: July 30, 2014Publication date: February 4, 2016Inventor: David P. Brunco
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Publication number: 20150340500Abstract: Embodiments of the present invention provide a semiconductor structure having a strain relaxed buffer, and method of fabrication. A strain relaxed buffer is disposed on a semiconductor substrate. A silicon region and silicon germanium region are disposed adjacent to each other on the strain relaxed buffer. An additional region of silicon or silicon germanium provides quantum well isolation.Type: ApplicationFiled: May 20, 2014Publication date: November 26, 2015Applicant: GLOBALFOUNDRIES Inc.Inventor: David P. Brunco
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Patent number: 8828839Abstract: Fabrication methods for semiconductor device structures are provided. In an exemplary embodiment, a method of fabricating an electrically-isolated FinFET semiconductor device includes the steps of forming a silicon oxide layer over a semiconductor substrate including a silicon material and forming a first hard mask layer over the silicon oxide layer. The method further includes the steps of forming a first plurality of void spaces in the first hard mask layer and forming a second hard mask layer in the first plurality of void spaces. Still further, the method includes the steps of removing the remaining portions of the first hard mask layer, thereby forming a second plurality of void spaces in the second hard mask layer, extending the second plurality of void spaces into the silicon oxide layer, and forming a plurality of fin structures in the extended second plurality of void spaces.Type: GrantFiled: January 29, 2013Date of Patent: September 9, 2014Assignee: GLOBALFOUNDRIES, Inc.Inventors: David P. Brunco, Witold Maszara
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Publication number: 20140213033Abstract: Fabrication methods for semiconductor device structures are provided. In an exemplary embodiment, a method of fabricating an electrically-isolated FinFET semiconductor device includes the steps of forming a silicon oxide layer over a semiconductor substrate including a silicon material and forming a first hard mask layer over the silicon oxide layer. The method further includes the steps of forming a first plurality of void spaces in the first hard mask layer and forming a second hard mask layer in the first plurality of void spaces. Still further, the method includes the steps of removing the remaining portions of the first hard mask layer, thereby forming a second plurality of void spaces in the second hard mask layer, extending the second plurality of void spaces into the silicon oxide layer, and forming a plurality of fin structures in the extended second plurality of void spaces.Type: ApplicationFiled: January 29, 2013Publication date: July 31, 2014Applicant: GLOBALFOUNDRIES, INC.Inventors: David P. Brunco, Witold Maszara