Abstract: A data link processor, which is basically a peripheral-controller for interfacing a main host computer system to a peripheral terminal unit, forms part of an I/O subsystem in which a base module unit houses a plurality of such peripheral-controllers (data link processors). Each base module carries a distribution control circuit card which provides a communication interface between the main host computer and the peripheral-controller. Each base module also carries a maintenance test circuit card for diagnostic testing of the peripheral-controllers. A data flow control circuit means controls direction of data transfer (a) between the host computer and peripheral-controller and (b) between the maintenance test circuit and the peripheral-controller.

Abstract: A specialized peripheral-controller, designated as a data link processor, is used in an I/O subsystem to control data transfers from a main host computer into a peripheral train-printer mechanism. The peripheral-controller has a RAM buffer memory with a pluraity of addressable locations. Each addressable memory location stores two characters designated as the top character and the bottom character.

Abstract: A specialized peripheral controller for controlling data transfers between a main host computer and a train printer mechanism is provided with a peripheral control interface circuit to control and monitor the printing of data and the paper format for the train printer mechanism. The peripheral control interface circuit includes a printer column timing pulse generator for enabling the train printer mechanism to scan over each column of its available printing area at least twice during each revolution of a train module which carries graphic character sets that will imprint upon the paper train when struck by a print-hammer within the train printer. The peripheral control interface circuit also includes control means to start and stop the motor of the train printer, means to select whether output data signals are for printout selection or for paper format control, and means to receive and sense condition information signals from the train printer mechanism.

Abstract: A peripheral-controller, designated as a Train Printer-Data Link Processor, provides the control interface between a main host computer and a train printer mechanism. A plurality of such peripheral-controllers make up an I/O subsystem whereby a main host computer is relieved of housekeeping duties in regard to peripheral units. This train printer data link processor (peripheral-controller) is made up of two slide-in circuit cards. The first card, known as the common front end (CFE) provides micro-code word operators for data transfer and printing operations in addition to supplying a specialized RAM buffer memory for storing data words from the main memory of the main host computer and selecting these words for printing in the attached peripheral device known as a train printer mechanism.

Abstract: A specialized RAM buffer memory is provided to work in conjunction with a peripheral-controller designated as a train printer-data link processor. The RAM buffer memory has addressable locations holding two 8-bit bytes at each addressable location. Thus, each addressable location has a top byte and a bottom byte, each of which represents a graphic character. A first dedicated portion of the buffer storage memory is called the print image buffer (PIB). This buffer is loaded with character data according to the number of print columns used in the train printer. When the print image buffer is loaded with character information, it constitutes one full line of print across the 132 columns. A second dedicated area of the memory buffer is called the train image buffer (TIB). This buffer is loaded with codes for the character set that matches the current print train module used in the train printer.

Abstract: A data link processor, which is basically a peripheral-controller for interfacing a main host computer system to a peripheral terminal unit, forms part of an I/O subsystem in which a base module unit houses a plurality of such peripheral-controllers (data link processors). Each base module carries a distribution control circuit card which provides a communication interface between the main host computer and the peripheral-controller. A special line turn-around logic circuit is used to control the direction of data flow as between the distribution control circuit card and the data link processor. In one direction, data may flow from the distribution control circuit card (originating from the main host computer) into the data link processor. In the other direction, information and status data can flow from the data link processor to the distribution control circuit card (and then to the main host computer).