Patents by Inventor David P. Chan

David P. Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5328865
    Abstract: A method for making an anti-fuse structure characterized by the steps of forming a conductive base layer; forming an anti-fuse layer over the base layer; patterning the anti-fuse layer to form an anti-fuse island; forming an insulating layer over the anti-fuse island; forming a via hole through the insulating layer to the anti-fuse island; forming a conductive connection layer over the insulating layer and within the via hole; and patterning the conductive connection layer to form a conductive contact to the anti-fuse island. Preferably, the anti-fuse island comprises amorphous silicon which can optionally be covered with a thin layer of a titanium-tungsten alloy.
    Type: Grant
    Filed: January 29, 1993
    Date of Patent: July 12, 1994
    Assignee: VLSI Technology, Inc.
    Inventors: William J. Boardman, David P. Chan, Kuang-Yeh Chang, Calvin T. Gabriel, Vivek Jain, Subhash R. Nariani
  • Patent number: 5290734
    Abstract: An anti-fuse structure characterized by a substrate, an oxide layer formed over the substrate having an opening formed therein, an amorphous silicon material disposed within the opening and contacting the substrate, a conductive protective material, such as titanium tungsten, disposed over the amorphous silicon material, and oxide spacers lining the walls of a recess formed within the protective material. The protective material and the spacers provide tighter programming voltage distributions for the anti-fuse structure and help prevent anti-fuse failure.
    Type: Grant
    Filed: July 26, 1991
    Date of Patent: March 1, 1994
    Assignee: VLSI Technology, Inc.
    Inventors: William J. Boardman, David P. Chan, Kuang-Yeh Chang, Calvin T. Gabriel, Vivek Jain, Subhash R. Nariani
  • Patent number: 5120679
    Abstract: An anti-fuse structure characterized by a substrate, an oxide layer formed over the substrate having an opening formed therein, an amorphous silicon material disposed within the opening and contacting the substrate, and oxide spacers lining the walls of a recess formed within the amorphous silicon. The spacers prevent failures of the anti-fuse structures by covering cusps formed in the amorphous silicon material. The method of the present invention forms the above-described anti-fuse structure and further solves the problem of removing unwanted spacer material from areas outside of the anti-fuse structure locations.
    Type: Grant
    Filed: June 4, 1991
    Date of Patent: June 9, 1992
    Assignee: VLSI Technology, Inc.
    Inventors: William J. Boardman, David P. Chan, Kuang-Yeh Chang, Calvin T. Gabriel, Vivek Jain, Subhash R. Nariani