Abstract: Techniques are described for a method for detecting a fault. The method includes receiving, by a receiving electronic device, via a differential pair transmission line, from a transmitting electronic device, an electrical signal. The method further includes converting, by a receiving (Rx) serializer/deserializer (SerDes) operating at the receiving electronic device, the received electrical signal into a received digital electrical signal. The method further includes, determining, by one or more processors, an electrical signature of the received electrical signal from the received digital electrical signal when the received electrical signal is received by the receiving electronic device. The method further includes determining, by the one or more processors, based on the electrical signature, a position of a fault between the receiving electronic device and the transmitting electronic device. The fault causes the received electrical signal to be different than the transmitted electrical signal.

Abstract: A printed circuit board (PCB) assembly may include a component capable of sending or receiving high-speed differential signal pairs, a package that is connected to the component, and a PCB connected to the package. The PCB assembly may be used to support a first high-speed differential signal pair that includes a first differential signal and a second differential signal. The first differential signal may be capable of causing crosstalk onto a particular differential signal, of a second high-speed differential signal pair, while propagating through the PCB assembly. A set of interconnects may be used to intelligently route the first differential signal pair within the package and/or within the PCB. The set of interconnects may include a first interconnect to route the first differential signal away from the particular differential signal and a second interconnect to route the second differential signal toward the particular differential signal.

Abstract: An apparatus may include via pads and grid array pads associated with facilitating a connection through a package and to a component, and vias that are electrically connected to the via pads, wherein the vias are used to support high-speed differential signal pairs that are capable of causing crosstalk onto other high-speed differential signal pairs while propagating through the package. The apparatus may include interconnects that electrically connect the vias to the grid array pads, and that are capable of routing the high-speed differential signal pairs in a way that offsets the crosstalk that the high-speed differential signal pairs are capable of causing while propagating through the package. The apparatus may include additional interconnects that electrically connect the vias to additional vias that are to be used to facilitate routing the high-speed differential signal pairs to the component, without the high-speed differential signal pairs propagating through a printed circuit board.

Abstract: In some examples, an electronic device includes a printed circuit board (PCB) device that includes a first trace electrically connected to a first pad of a first trace via on a first layer and a second trace electrically connected to a second pad of a second trace via on a second layer. In some examples, the PCB device also includes four ground pads on the first layer and an antipad surrounding the two trace vias, where a first ground pad is positioned between the first trace and the second trace, where the first ground pad and the second ground pad are approximately symmetrically positioned about a perpendicular bisector of a line from the first pad to the second pad, and wherein the third ground pad and the fourth ground pad are approximately symmetrically positioned about the perpendicular bisector of the line from the first pad to the second pad.

Abstract: Techniques are described for a method for detecting a fault. The method includes receiving, by a receiving electronic device, via a differential pair transmission line, from a transmitting electronic device, an electrical signal. The method further includes converting, by a receiving (Rx) serializer/deserializer (SerDes) operating at the receiving electronic device, the received electrical signal into a received digital electrical signal. The method further includes, determining, by one or more processors, an electrical signature of the received electrical signal from the received digital electrical signal when the received electrical signal is received by the receiving electronic device. The method further includes determining, by the one or more processors, based on the electrical signature, a position of a fault between the receiving electronic device and the transmitting electronic device. The fault causes the received electrical signal to be different than the transmitted electrical signal.

Abstract: In some examples, an electronic device includes a printed circuit board (PCB) device that includes a first trace electrically connected to a first pad of a first trace via on a first layer and a second trace electrically connected to a second pad of a second trace via on a second layer. In some examples, the PCB device also includes four ground pads on the first layer and an antipad surrounding the two trace vias, where a first ground pad is positioned between the first trace and the second trace, where the first ground pad and the second ground pad are approximately symmetrically positioned about a perpendicular bisector of a line from the first pad to the second pad, and wherein the third ground pad and the fourth ground pad are approximately symmetrically positioned about the perpendicular bisector of the line from the first pad to the second pad.

Abstract: In an example of this disclosure, a method may include receiving, by a bit error location analyzer, a split information signal at a second data rate derived from an information signal at a first data rate. In this example, the second data rate is less than the first data rate, and the bit error location analyzer may be incapable of performing error analysis at the first data rate The method may include performing error analysis, by the bit error location analyzer, on information represented by the split information signal. In some examples, performing error analysis may include comparing the information represented by the split information signal to an information seed to determine a plurality of bit error locations in the information represented by the split information signal relative to the information seed.

Abstract: In general, techniques are described that insert one or more bits into a digital bit stream to maintain an overall transition density in the digital bit stream. Maintaining the overall transition density facilitates the generation of a recovered clock by a phase-locked loop (PLL) circuit of a receiver. For example, when a data transition ratio for a portion of the digital bit stream is less than a desired data transition ratio, the techniques insert additional bits to increase the overall transition density of the digital bit stream.

Abstract: A multi-interface bus allows for different bus standards to be implemented over the same set of physical bus lines. More particularly, in one implementation, the system includes a first circuit board, a second circuit board, and a bus connecting the first and second circuit boards. The second circuit board is configured to communicate with the first circuit board using either a synchronous or an asynchronous bus protocol determined based on a bus protocol used by the first circuit board.

Abstract: A device provides a time domain reflectometry (TDR) or a vector network analyzer (VNA) test signal to a via test area provided on a printed circuit board (PCB), where the via test area includes vias and via stubs formed in the vias. The device also receives a reflected signal from each via in the via test area of the PCB, and compares the reflected signal from each via to a minimum impedance threshold. The device further provides, for display, an indication of passing for the PCB, when the reflected signals from the vias are greater than the minimum impedance threshold.

Abstract: A device applies synchronous clocking across a first component and a second component of the device, and designates a particular serial link, from a group of serial links, as a master serial link. The device also designates the remaining serial links as slave serial links, provides, via the master serial link, an encoded data stream, and provides, via the slave serial links, un-encoded and scrambled data streams.

Abstract: A multi-interface bus allows for different bus standards to be implemented over the same set of physical bus lines. More particularly, in one implementation, the system includes a first circuit board, a second circuit board, and a bus connecting the first and second circuit boards. The second circuit board is configured to communicate with the first circuit board using either a synchronous or an asynchronous bus protocol determined based on a bus protocol used by the first circuit board.

Abstract: An isolation switch is used to isolate the output of an oscillator, during startup of the oscillator, from the circuitry that uses the periodic signal generated by the oscillator. In one implementation, a device may include an oscillator to generate a periodic signal and a switch connected to receive an output of the oscillator. The switch may include a control input that controls whether the switch is in an open or closed state. Switch control circuit may control the switch so that the switch is in an open state during startup of the oscillator and the switch is in a closed state thereafter.

Abstract: A system for testing link performance margin in a network device includes one or more daughter cards having a driver to transmit a signal and a receiver to receive the signal, and a midplane including a channel to transmit the signal from the driver to the receiver. The system includes multiple connector assemblies to connect the one or more daughter cards to the midplane, where each of the multiple connector assemblies includes a different known crosstalk margin value. A bit error rate tester is connected to a link between the driver and the receiver, and the multiple connector assemblies are interchangeably included in the link to approximate different signal-to-noise ratio margins for the tested link.

Abstract: An isolation switch is used to isolate the output of an oscillator, during startup of the oscillator, from the circuitry that uses the periodic signal generated by the oscillator. In one implementation, a device may include an oscillator to generate a periodic signal and a switch connected to receive an output of the oscillator. The switch may include a control input that controls whether the switch is in an open or closed state. Switch control circuit may control the switch so that the switch is in an open state during startup of the oscillator and the switch is in a closed state thereafter.

Abstract: A device applies synchronous clocking across a first component and a second component of the device, and designates a particular serial link, from a group of serial links, as a master serial link. The device also designates the remaining serial links as slave serial links, provides, via the master serial link, an encoded data stream, and provides, via the slave serial links, un-encoded and scrambled data streams.

Abstract: A processor-inclusive memory module (PIMM) is disclosed. In one embodiment of the present invention, the PIMM includes a printed circuit board having first and second opposing surfaces. The printed circuit board also has an address line formed therein. A first SRAM is mounted on the first surface of the printed circuit board. The present PIMM is further comprised of a second SRAM mounted on the second surface of the printed circuit board. The second SRAM is mounted on the second surface of the printed circuit board directly opposite the first SRAM mounted on the first surface of the printed circuit board. The first and second SRAMs are coupled to the address line by respective cache buses. A processor is also mounted on the first surface of the printed circuit board, and is coupled to the address line. In one embodiment of the invention, a heat sink is thermally coupled to the processor. The processor has a plurality of contact pads disposed thereon.

Abstract: A processor-inclusive memory module (PIMM) is disclosed. In one embodiment of the present invention, the PIMM includes a printed circuit board having first and second opposing surfaces. The printed circuit board also has an address line formed therein. A first SRAM is mounted on the first surface of the printed circuit board. The present PIMM is further comprised of a second SRAM mounted on the second surface of the printed circuit board. The second SRAM is mounted on the second surface of the printed circuit board directly opposite the first SRAM mounted on the first surface of the printed circuit board. The first and second SRAMs are coupled to the address line by respective cache buses. A processor is also mounted on the first surface of the printed circuit board, and is coupled to the address line. In one embodiment of the invention, a heat sink is thermally coupled to the processor. The processor has a plurality of contact pads disposed thereon.

Abstract: A multi-configurable HSTL/LVCMOS/Open-Drain output driver circuit includes push-pull and open-drain transistors that are selectively enabled/disabled depending upon the desired mode of operation.

Abstract: The present invention incorporates a variable delay circuit to add delay to a clock signal. In a preferred embodiment of the present invention, the delay is determined and fixed by a circuit employing the concept of a lock-and-leave circuit. This has the effect of fine tuning the delay determined by the lock-and-leave circuit. Mode bits allow a user to control the rate at which fine tuning occurs. Three update rates are provided in a preferred embodiment of the present invention. They are slow, medium, and fast.