Abstract: An integrated circuit has a plurality of programmable antifuses. Each antifuse can be programmed to connect metals runners on one level with either or both of a pair of runners on a second level.

Abstract: A layer of spin-on-glass is used as a hard mask for patterning an underlying layer of polysilicon. The patterned polysilicon may be used in the gate structures of field effect transistors.

Abstract: Self-aligned contacts are formed to regions between closely spaced features by a method which uses differential etch rates between first and second dielectrics deposited over the closely spaced features.

Abstract: A polysilicon self-aligned transistor has a polysilicon layer (24) with a cavity (30) formed therein. To form the polysilicon layer (24) with a cavity (30), a thin seed layer (14) is disposed over an epitaxial layer (11a). Dielectric layers (16, 18) are formed over the seed layer (14), and are subsequently etched to define the polysilicon layer (24) and the cavity (30). The cavity (30) is defined by a dielectric plug (22). The exposed seed layer (14) is used to selectively grow the polysilicon layer (24). Thereafter, the dielectric plug (22) is removed to form the cavity (30) through which the base (32) is implanted into the substrate (12) and the emitter (36) is formed.

Abstract: An integrated circuit design and method for its fabrication are disclosed. A bilevel-dielectric is formed to cover the active regions of a transistor and raised topographic features such as a gate runner. The upper level of the dielectric is planarized to provide for easier subsequent multilevel-conductor processing. Windows are opened in the bilayer dielectric by etching through the upper level of the dielectric, stopping on the lower level of the dielectric. Then the etch procedure is continued to etch through the lower level of the dielectric.

Abstract: A single layer polysilicon self-aligned transistor (52) is provided having a substantially vertical emitter contact region (62), such that the emitter contact region (62) does not require extending portions overlying the base region (60). Heavily doped silicided regions (68) are disposed adjacent the emitter (64) in a self-aligned process such that the base resistance of the device is minimized. A planar oxide layer (72) is formed such that the emitter contact region (62) are exposed without exposing other polysilicon gates of the integrated circuit. A metal layer (76) may be disposed over the planar oxide layer (72) to form a level of interconnects.

Abstract: A polysilicon self-aligned transistor has a polysilicon layer (24) with a cavity (30) formed therein. To form the polysilicon layer (24) with a cavity (30), a thin seed layer (14) is disposed over an epitaxial layer (11a). Dielectric layers (16, 18) are formed over the seed layer (14), and are subsequently etched to define the polysilicon layer (24) and the cavity (30). The cavity (30) is defined by a dielectric plug (22). The exposed seed layer (14) is used to selectively grow the polysilicon layer (24). Thereafter, the dielectric plug (22) is removed to form the cavity (30) through which the base (32) is implanted into the substrate (12) and the emitter (36) is formed.