Abstract: The present disclosure provides for synchronization of multi-core systems by monitoring a plurality of debug trace data streams for a redundantly operating system including a corresponding plurality of cores performing a task in parallel; in response to detecting a state difference on one debug trace data stream of the plurality of debug trace data streams relative to other debug trace data streams of the plurality of debug trace data streams: marking a given core associated with the one debug trace data stream as an affected core; and restarting the affected core.

Abstract: The present disclosure provides for synchronization of multi-core systems by monitoring a plurality of debug trace data streams for a redundantly operating system including a corresponding plurality of cores performing a task in parallel; in response to detecting a state difference on one debug trace data stream of the plurality of debug trace data streams relative to other debug trace data streams of the plurality of debug trace data streams: marking a given core associated with the one debug trace data stream as an affected core; and restarting the affected core.

Abstract: Apparatuses and methods for utilizing error correction code in a data buffer or data storage device. In one variation, a single memory device is utilized to store both the data and the associated error correction code. The data and the associate error correction codes are stored on separate memory banks on the memory device. The error correction code may be consolidated into one or more regions on the memory device to improve the utilization of the available memory space on the memory device. In addition, by utilizing separate memory banks to store the data and the associated error correction code, the data and the error correction code can be accessed in an overlapping manner.

Abstract: A circuit for measuring voltage of a battery or group of batteries whose terminals are not directly accessible. The battery or group of batteries can have three leads. First and second leads are connected to the voltage output of the battery and the third lead is connected to the return of the battery. The three leads may terminate in a three prong plug which may plug into a printed circuit board to form a module. The module can be connected into a rack via an edge connector. A battery voltage measurement circuit can be located on another printed circuit board which is also plugged into the rack. This other printed circuit board may be interconnected to the battery module by wire traces within the rack. Thus, there are one or more first connectors between the first lead of the battery or group of batteries and the charger. There are one or more second connectors between the second lead of the battery or group of batteries and an input of the voltage measurement circuit.

Abstract: A circuit for measuring voltage of a battery or group of batteries whose terminals are not directly accessible. The battery or group of batteries can have three leads. First and second leads are connected to the voltage output of the battery and the third lead is connected to the return of the battery. The three leads may terminate in a three prong plug which may plug into a printed circuit board to form a module. The module can be connected into a rack via an edge connector. A battery voltage measurement circuit can be located on another printed circuit board which is also plugged into the rack. This other printed circuit board may be interconnected to the battery module by wire traces within the rack. Thus, there are one or more first connectors between the first lead of the battery or group of batteries and the charger. There are one or more second connectors between the second lead of the battery or group of batteries and an input of the voltage measurement circuit.

Abstract: The dynamically mapped data storage subsystem generates a two error correction, three error detection code of extent sufficient to cover not only the data but also the corresponding memory address for each data record stored therein. The error correction code is transmitted and stored with the data within the data storage subsystem to ensure the integrity of both the data and its memory address.

Abstract: The data storage subsystem of the present invention uses a large plurality of small form factor disk drives to implement an inexpensive, high performance, high reliability disk drive memory that emulates the format and capability of large form factor disk drives. The data transmitted by the associated computer system is used to generate redundancy information which is written with the data across N+M disk drives in a redundancy group in the data storage subsystem. To clear the redundancy accumulator memory, an associated pointer memory is used to indicate the ones of the redundancy accumulator memory byte positions that were used in the previous redundancy calculation. As data is received from the computer system, the pointer memory is checked to determine whether this next byte position need be reset to erase the previously stored redundancy calculation residue. If not, the data is simply stored therein.