Abstract: An ASIC is disclosed that is formed on a die with multiple functional blocks distributed on the die, each functional block being able to send and to receive data, and each having two inputs labeled slow and fast. The slow input may have a delay component that creates a delay in receiving a data signal, and the fast input may have less delay than the slow input. A switch may be used to couple the slow input and the fast input of a receiving functional block to a data signal based on a distance of the receiving functional block from a sending functional block. The delay in the slow input is used to adjust input data timing to meet setup and hold timing specifications of the functional blocks without altering the ASIC circuit components aside from the functional blocks.

Abstract: A system, includes a plurality of sub-queues. Each sub-queue is assigned to an age class of a sequence of age classes. A set of age thresholds divides the sub-queues. A queue manager places a received transaction into a sub-queue based on a comparison of an age of the received transaction to the set of age thresholds.

Abstract: A system, includes a plurality of sub-queues. Each sub-queue is assigned to an age class of a sequence of age classes. A set of age thresholds divides the sub-queues. A queue manager places a received transaction into a sub-queue based on a comparison of an age of the received transaction to the set of age thresholds.

Abstract: The present invention relates to a system and method for establishing an illegal system state for a table which is preferably fully associative to disable matching of prospective entries (entries to be written to the table) with entries already resident in the table. Preferably, disabling the matching of prospective and table entries forces a system for updating the fully associative table or array to employ a pointer system for writing prospective entries into the fully associative table. The illegal system may be invoked automatically upon powering up the system for updating the fully associative array or may be associated with a machine specific state effected upon issuing a specific command during program execution.

Abstract: The present invention relates to a mechanism for updating a fully associative array which is used to store entries associated with speculated instructions. Preferably, the array includes a plurality of data banks for storing entries, a plurality of ports for writing to the plurality of data banks, pointers associated with the respective banks for identifying table locations suitable for overwriting by upcoming entries, wherein an entry is suitable for overwriting when it is deemed invalid by the inventive system. A preferred embodiment is disclosed involving two ports writing to two banks wherein a plurality of factors is considered in deciding where prospective entries from the two ports will be written in the table. The Factors include, matches between existing and prospective entries, the default designated data bank for a given port, whether two write operations are being attempted simultaneously, and the number of entries already present in each data bank.

Abstract: The present invention relates to a system and method for establishing an illegal system state for a table which is preferably fully associative to disable matching of prospective entries (entries to be written to the table) with entries already resident in the table. Preferably, disabling the matching of prospective and table entries forces a system for updating the fully associative table or array to employ a pointer system for writing prospective entries into the fully associative table. The illegal system may be invoked automatically upon powering up the system for updating the fully associative array or may be associated with a machine specific state effected upon issuing a specific command during program execution.

Abstract: The present invention discloses a system and method for simultaneously identifying a most recent advanced load instruction employing a particular register and determining whether the instruction conflicts with a store instruction thereby requiring a recovery operation. Fully associative tables are advantageously employed for identifying the most recent load instruction, for comparing store instruction address information with addresses employed in advanced load instructions, and for logging a validity status associated with a register number. Parallel operation of load vs. check register numbers and load instruction and store instruction memory addresses conserves time and preferably enables a hit/miss determination for a particular check instruction to be completed in single machine cycle.

Abstract: A CMOS latch with improved immunity to soft errors resulting from energetic particle strikes is disclosed. In one embodiment two Schmitt triggers are cross-coupled to hold a logic state. The significant hysteresis of the Schmitt triggers improves the resistance of the latch to induced soft errors. In a further embodiment, the Schmitt triggers operate by providing feedback from the Schmitt trigger output that changes the effective impedance of both the pullup and pulldown networks of the Schmitt trigger thereby creating significant hysteresis. In another embodiment, the Schmitt triggers operate by providing feedback from the Schmitt trigger output that changes the effective impedance of only one of either the pullup or pulldown network of the Schmitt trigger thereby creating significant hysteresis.

Abstract: A three state, dual port CAM cell responsive to three combinations, i.e., 0,0 and 1,0 and 0,1, of two binary inputs includes a pair of latches, each having a pair of inverters connected in a regenerative feedback circuit. For the 0,0 combination, a driver and FET disable the second inverter in such a way that output tenninals of the latches supply 0,0 to a pair of data lines. For the 1,0 combination, both inverters of both latches are enabled, causing the latches to supply the data lines with 1,0. For the 0,1 combination, the second inverter is disabled in such a way that the output terminals of the latches supply the data lines with 0,1.

Abstract: A content addressable memory (CAM) has a matrix of dual port memory cells each storing two encoded bits resulting from a data bit being combined with a mask bit. The encoded bits have differing values representing the data bit value when the cell is not masked and the same values when the cell is masked. During a CAM look-up operation when the encoded bits indicate the cell is not masked, a matching circuit of the cell compares the encoded bits and a reference bit so an output of the matching circuit indicates whether the data bit which resulted in the stored encoded bits is the same as the reference bit. When the cell is read by an address word and the encoded bits indicate the cell is not masked, the cell drives a read port with a level indicative of the data bit which resulted in the encoded bits. When the encoded bits indicate the cell is masked, the outputs of matching circuit and the read port are static.