Abstract: A noise immunity circuit has a distributed electrical plane to which noise susceptible components are coupled. Also, in a close proximity are noise generating circuits that generate electrical noise onto the distributed electrical plane that affect the noise susceptible components. A coupling means is used to couple the noise susceptible circuits to the distributed electrical plane so that the noise of the distributed electrical plane is common to all points in the noise susceptible circuit. Also, inputs and power to the circuit are coupled to the distributed electrical plane so that the common noise is imposed upon them. Coupling preferably takes place through a variety of capacitors and resistors so that high frequency noise is coupled to the noise susceptible circuit.

Abstract: A circuit and method of demodulating an FSK signal uses digital circuitry to convert the received signal into count values. For each reception an adaptive reference count value is determined by averaging the duration of received pulses during the preamble of the transmission. The adaptive reference count corresponds to a demodulated logic "1" or logic level "0". The counts from the coded portion of the transmission are compared to the adaptive reference count. If the count is within predetermined windows from the reference count, the count value is converted to the corresponding digital signal.

Abstract: A method and circuit for generating an output signal representative of the pumping current required to equalize the oxygen diffusion between the sensing cell and the pumping cell of an oxygen-ion concentration proportional sensor located in the exhaust system of an internal combustion engine. A replication current, which is isolated from but representative of the pumping current, is generated. The replication current is then passed through a load resistance for generating the output signal. The replication current is generated simultaneously with but isolated from the pumping current, thereby eliminating the need for separate amplification of a sensed version of the pumping current.

Abstract: A CMOS comparator has programmable hysteresis using a differential pair of MOS transistors, a current mirror pair of transistors and a feedback path which is function of comparator output, MOSFET threshold voltage and digitally selectable inputs. The comparator has characteristics suitable for sensing and processing low level signals from a variable reluctance sensor in an electrically noisy environment.

Abstract: A GaAs logic circuit uses a first FET to control the application of a logic signal from an input to an output. The first FET inherently has parasitic gate-to-source and gate-to-drain diodes. A control signal applied to the gate of the first FET controls the application of the logic signal to the output through the first FET. For a first FET that is an enhancement mode GaAs device, the gate current tends to forward bias such diodes under all operating conditions and tends to significantly increase the gate current. For a first FET that is a depletion-mode device, adverse operating temperatures can cause such tendency to forward bias these diodes and other circuit diodes. A limiter FET connected to the gate to limit the gate current and thus limits the forward biasing of the parasitic and circuit diodes. This reduces the effect on the gate current of variations in the power supplies to the FET, process variations and operating temperature variations.

Abstract: A low noise, high precision differential amplifier has an input bias and noise current cancellation circuit which includes a sensing device connected between common terminals of the differential pair and a reference potential. The sensing device is connected to a feedback circuit for supplying a bias and noise cancellation current to the amplifier inputs. The sensing device is constructed from a pair of matched transistors, which are also matched to the input differential pair. The feedback circuit includes two current mirrors constructed from four identically matched devices. A Darlington pair is located in the collector leg of each input transistor to improve the common mode rejection ratio. Added noise reduction is achieved by implementing the circuit with low surface noise transistors. A preferred embodiment of the circuit includes a resistance network for adjusting the bias voltages on the gates of the low surface noise transistors.

Abstract: A controlled current limiter having a diode in series with the voltage divider of the current limiting transistor to prevent power dissipation during idle conditions. A switch responsive to the output current is in series with the diode. A clamp responsive to preselected voltage differences clamps the limited current to a fixed valve.