Patents by Inventor David P. Price

David P. Price has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • IC testing methods and apparatus
    Patent number: 8327205
    Abstract: A method is provided for testing an integrated circuit comprising multiple cores, with at least two cores having different associated first and second clock signals of different frequencies. A test signal is provided using a clocked scan chain clocked at a test frequency (TCK). A transition is provided in a clock circuit reset signal (clockdiv_rst) which triggers the operation of a clock divider circuit (44) which derives the first and second clock signals (clk_xx, clk_yy, clk_zz) from an internal clock (40) of the integrated circuit. The first and second clock signals thus start at substantially the same time, and these are used during a test mode to perform a test of the integrated circuit. After test, the test result is output using the clocked scan chain clocked at the test frequency (TCK).
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: December 4, 2012
    Assignee: NXP B.V.
    Inventors: Tom Waayers, Johan C. Meirlevede, David P. Price, Norbert Schomann, Ruediger Solbach, Hervé Fleury, Jozef R. Poels
  • Ic Testing Methods and Apparatus
    Publication number: 20090003424
    Abstract: A method is provided for testing an integrated circuit comprising multiple cores, with at least two cores having different associated first and second clock signals of different frequencies. A test signal is provided using a clocked scan chain clocked at a test frequency (TCK). A transition is provided in a clock circuit reset signal (clockdiv_rst) which triggers the operation of a clock divider circuit (44) which derives the first and second clock signals (clk_xx, clk_yy, clk_zz) from an internal clock (40) of the integrated circuit. The first and second clock signals thus start at substantially the same time, and these are used during a test mode to perform a test of the integrated circuit. After test, the test result is output using the clocked scan chain clocked at the test frequency (TCK).
    Type: Application
    Filed: January 4, 2007
    Publication date: January 1, 2009
    Applicant: NXP B.V.
    Inventors: Tom Waayers, Johan C. Meirlevede, David P. Price, Norbert Schomann, Ruediger Solbach, Herve Fleury, Jozef R. Poels
  • Delay fault test circuitry and related method
    Patent number: 6996759
    Abstract: The invention provides for a delay fault testing method and related circuitry for producing a test pulse in response to an input clock signal, and including analysing first and second clock signals having different frequencies and associated with logic circuits having different application speeds, generating a train of two clock pulses for each of the said first and second clock signals, the train of clock pulses being arranged such that the rising edges of the second pulses in each of the said trains are aligned.
    Type: Grant
    Filed: July 25, 2002
    Date of Patent: February 7, 2006
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: David P. Price
  • Delay fault test circuitry and related method
    Publication number: 20030101396
    Abstract: The invention provides for a delay fault testing method and related circuitry for producing a test pulse in response to an input clock signal, and including analysing first and second clock signals having different frequencies and associated with logic circuits having different application speeds, generating a train of two clock pulses for each of the said first and second clock signals, the train of clock pulses being arranged such that the rising edges of the second pulses in each of the said trains are aligned.
    Type: Application
    Filed: July 25, 2002
    Publication date: May 29, 2003
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventor: David P. Price