Abstract: Provided is a keyed running tool for use with a slotted orientation apparatus. The keyed running tool, in one aspect, includes a housing, and two or more keys extending from the housing, the two or more keys movable between a radially retracted state and a radially extended state, wherein adjacent ones of the two or more keys are laterally offset from each other and radially offset from each other by Y degrees, wherein Y is 180 degrees or less.

Abstract: Techniques are disclosed relating to multiway communications. In some embodiments, a first electronic device initiates a multiway call between a plurality of electronic devices and exchanges a first secret with a first set of electronic devices participating during a first portion of the multiway call, the first secret being used to encrypt traffic between the first set of electronic devices. The first electronic device receives an indication that first set of participating electronic devices has changed and, in response to the indication, exchanges a second secret with a second set of electronic devices participating during a second portion of the multiway call, the second secret being used to encrypt traffic between the second set of participating electronic devices. In some embodiments, the indication identifies a second electronic device as leaving the multiway call, and the second secret is not exchanged with the second electronic device.

Abstract: 3An optimal delay value, usually the mid-delay in the operational window, for the data signal may be retained as a way of shifting the skew of the clock on all data lines at the same time. That delay value may be stored in a memory and converted to a control voltage for controlling a digitally controlled voltage variable delay to adjust the delay for data in a bus. The digitally controlled voltage variable delay contains a number of individual delay units which are selectively activated by the control voltage from the value stored in memory. A phase locked loop is employed to ensure that variations due to voltage, temperature, and processing are minimized.

Abstract: A transient immune bistable input buffer circuit. The circuit comprises a filter connected between an input and a reference voltage terminal to the circuit for reducing the sensitivity of the circuit to a voltage transient on the terminal.

Abstract: A buffer circuit with controlled output switching rate suitable to suppress ground or power supply line voltage spikes attributable to current surges. The voltage driving the gate electrode of the selected CMOS inverter output transistor is controlled in rate of rise using three parallel connected sources of charging current. The first source of current is enabled immediately following the step input signal to provide a relatively high initial rate of current flow and corresponding voltage rise on the gate electrode of the output transistor, but is self-disabled at approximately half the supply voltage by threshold loss and body effect on the transistor supplying the first source of current. The succeeding time interval is characterized by a slow rate of rise of the output transistor gate voltage attributable to a small but continuous source of current to the output transistor gate electrode node.