Abstract: An integrated circuit (IC), including: a metal-oxide-semiconductor (MOS) capacitor coupled between a first voltage rail and a node, wherein the MOS capacitor generates a leakage current while in operation, the leakage current flowing between the first voltage rail and the node; and a capacitor leakage-current compensation circuit coupled between the node and a second voltage rail, wherein the capacitor leakage-current compensation circuit is configured to generate a compensation current flowing between the node and the second voltage rail, the compensation current flowing in the same direction as the leakage current between the first voltage rail and the second voltage rail.

Abstract: An integrated circuit (IC), including: a metal-oxide-semiconductor (MOS) capacitor coupled between a first voltage rail and a node, wherein the MOS capacitor generates a leakage current while in operation, the leakage current flowing between the first voltage rail and the node; and a capacitor leakage-current compensation circuit coupled between the node and a second voltage rail, wherein the capacitor leakage-current compensation circuit is configured to generate a compensation current flowing between the node and the second voltage rail, the compensation current flowing in the same direction as the leakage current between the first voltage rail and the second voltage rail.

Abstract: A level-shifter is provided that balances the pull-up and pull-down of a pair of internal nodes. To balance the pull-down of the internal nodes, a pull-down strength of a pull-down network is also responsive to a power supply voltage for the level-shifter. To balance the pull-up of the internal nodes, a pull-up strength of a pull-up network is also responsive to an amplitude of an input signal being level-shifted by the level-shifter.