Patents by Inventor David Papworth
David Papworth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11294809Abstract: Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.Type: GrantFiled: August 28, 2018Date of Patent: April 5, 2022Assignee: Intel CorporationInventors: Jason W. Brandt, Robert S. Chappell, Jesus Corbal, Edward T. Grochowski, Stephen H. Gunther, Buford M. Guy, Thomas R. Huff, Christopher J. Hughes, Elmoustapha Ould-Ahmed-Vall, Ronak Singhal, Seyed Yahya Sotoudeh, Bret L. Toll, Lihu Rappoport, David Papworth, James D. Allen
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Patent number: 10469557Abstract: In one embodiment, Quality of Service (QoS) criteria based server side binary translation and execution of applications is performed on multiple servers utilizing distributed translation and execution in either a virtualized or native execution environment. The translated applications are executed to generate output display data, the output display data is encoded in a media format suitable for video streaming, and the video stream is delivered over a network to a client device. In one embodiment, one or more graphics processors assist the central processors of the servers by accelerating the rendering of the application output, and a media encoder encodes the application output into a media format.Type: GrantFiled: December 19, 2016Date of Patent: November 5, 2019Assignee: Intel CorporationInventors: Bharath Muthiah, William Rash, Glenn Hinton, Martin G. Dixon, Scott Hahn, David Papworth
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Patent number: 10282296Abstract: Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.Type: GrantFiled: December 12, 2016Date of Patent: May 7, 2019Assignee: Intel CorporationInventors: Jason W. Brandt, Robert S. Chappell, Jesus Corbal, Edward T. Grochowski, Stephen H. Gunther, Buford M. Guy, Thomas R. Huff, Elmoustapha Ould-Ahmed-Vall, Bret L. Toll, David Papworth, James D. Allen
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Publication number: 20190012266Abstract: Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.Type: ApplicationFiled: August 28, 2018Publication date: January 10, 2019Inventors: Jason W. Brandt, Robert S. Chappell, Jesus Corbal, Edward T. Grochowski, Stephen H. Gunther, Buford M. Guy, Thomas R. Huff, Christopher J. Hughes, Elmoustapha Ould-Ahmed-Vall, Ronak Singhal, Seyed Yahya Sotoudeh, Bret L. Toll, Lihu Rappoport, David Papworth, James D. Allen
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Publication number: 20180165199Abstract: Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a cache line sized write of zeros. The coherent cache is to receive the write command, to determine whether there is a hit in the coherent cache and whether a cache coherency protocol state of the hit cache line is a modified state or an exclusive state, to configure a cache line to indicate all zeros, and to issue the write command toward the interconnect. The interconnect is to, responsive to receipt of the write command, issue a snoop to each of a plurality of other coherent caches for which it must be determined if there is a hit.Type: ApplicationFiled: December 12, 2016Publication date: June 14, 2018Inventors: Jason W. Brandt, Robert S. Chappell, Jesus Corbal, Edward T. Grochowski, Stephen H. Gunther, Buford M. Guy, Thomas R. Huff, Christopher J. Hughes, Elmoustapha Ould-Ahmed-Vall, Ronak Singhal, Seyed Yahya Sotoudeh, Bret L. Toll, Lihu Rappoport, David Papworth, James D. Allen
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Publication number: 20170237797Abstract: In one embodiment, Quality of Service (QoS) criteria based server side binary translation and execution of applications is performed on multiple servers utilizing distributed translation and execution in either a virtualized or native execution environment. The translated applications are executed to generate output display data, the output display data is encoded in a media format suitable for video streaming, and the video stream is delivered over a network to a client device. In one embodiment, one or more graphics processors assist the central processors of the servers by accelerating the rendering of the application output, and a media encoder encodes the application output into a media format.Type: ApplicationFiled: December 19, 2016Publication date: August 17, 2017Inventors: Bharath Muthiah, William Rash, Glenn Hinton, Martin G. Dixon, Scott Hahn, David Papworth
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Patent number: 9525586Abstract: In one embodiment, Quality of Service (QoS) criteria based server side binary translation and execution of applications is performed on multiple servers utilizing distributed translation and execution in either a virtualized or native execution environment. The translated applications are executed to generate output display data, the output display data is encoded in a media format suitable for video streaming, and the video stream is delivered over a network to a client device. In one embodiment, one or more graphics processors assist the central processors of the servers by accelerating the rendering of the application output, and a media encoder encodes the application output into a media format.Type: GrantFiled: March 15, 2013Date of Patent: December 20, 2016Assignee: Intel CorporationInventors: Bharath Muthiah, William Bill Rash, Glenn Hinton, Martin G. Dixon, Scott Hayn, David Papworth
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Publication number: 20140281008Abstract: In one embodiment, Quality of Service (QoS) criteria based server side binary translation and execution of applications is performed on multiple servers utilizing distributed translation and execution in either a virtualized or native execution environment. The translated applications are executed to generate output display data, the output display data is encoded in a media format suitable for video streaming, and the video stream is delivered over a network to a client device. In one embodiment, one or more graphics processors assist the central processors of the servers by accelerating the rendering of the application output, and a media encoder encodes the application output into a media format.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: Bharath Muthiah, William Bill Rash, Glenn Hinton, Martin G. Dixon, Scott Hahn, David Papworth