Abstract: A system including a memory controller chiplet having a memory interface that is configured to couple the memory controller chiplet to first and second memory devices. The memory interface includes first and second memory channels having respective data widths, and configured to couple first and second I/O interfaces of the memory controller chiplet to an interface of the first memory device having a data channel width at least equal to the combined first and second memory channel widths, where the first and second memory channels have independent command/address (CA) paths; and third and fourth memory channels having respective data widths, and configured to couple third and fourth I/O interfaces of the memory controller chiplet to an interface of the second memory device having a data channel width at least equal to the combined third and fourth memory channel widths, wherein the third and fourth memory channels have independent CA paths.

Abstract: Devices and techniques for loading contexts in a coarse-grained reconfigurable array processor are described herein. A system or apparatus may include context load circuitry operable to load context for a coarse-grained reconfigurable array processor, where the context load circuitry is configured to: (a) receive a kernel identifier; (b) access a first registry to obtain a context mask base address; (c) determine a context mask address from the context mask base address and the kernel identifier; (d) access a second registry to obtain a context state base address; (e) determine a context state address from the context state base address and the kernel identifier; (f) use a context mask at the context mask address to determine corresponding active context state; and (g) load the corresponding active context state into the coarse-grained reconfigurable array processor.

Abstract: Devices and techniques for loading contexts in a coarse-grained reconfigurable array processor are described herein. A system or apparatus may include context load circuitry operable to load context for a coarse-grained reconfigurable array processor, where the context load circuitry is configured to: (a) receive a kernel identifier; (b) access a first registry to obtain a context mask base address; (c) determine a context mask address from the context mask base address and the kernel identifier; (d) access a second registry to obtain a context state base address; (e) determine a context state address from the context state base address and the kernel identifier; (f) use a context mask at the context mask address to determine corresponding active context state; and (g) load the corresponding active context state into the coarse-grained reconfigurable array processor.

Abstract: A credit return field is used in a credit-based flow control system to indicate that one or more credits are being returned to a sending device from a receiving device. Based on the number of credits available, the sending device determines whether to send device or wait until more credits are returned. A write enable mask allows a wide data field to be used even when a smaller amount of data is to be written. A novel data packet uses a combined write enable mask and credit return field. In one mode, the field contains a write enable mask. In another mode, the field contains credit return data. If the field contains credit return data, a default value (e.g., all ones) is used for the write enable mask. The mode may be selected based on another value in the data packet.

Abstract: A system including a memory controller chiplet having a memory interface that is configured to couple the memory controller chiplet to first and second memory devices. The memory interface includes first and second memory channels having respective data widths, and configured to couple first and second I/O interfaces of the memory controller chiplet to an interface of the first memory device having a data channel width at least equal to the combined first and second memory channel widths, where the first and second memory channels have independent command/address (CA) paths; and third and fourth memory channels having respective data widths, and configured to couple third and fourth I/O interfaces of the memory controller chiplet to an interface of the second memory device having a data channel width at least equal to the combined third and fourth memory channel widths, wherein the third and fourth memory channels have independent CA paths.

Abstract: A system including a memory controller chiplet having a memory interface that is configured to couple the memory controller chiplet to first and second memory devices. The memory interface includes first and second memory channels having respective data widths, and configured to couple first and second I/O interfaces of the memory controller chiplet to an interface of the first memory device having a data channel width at least equal to the combined first and second memory channel widths, where the first and second memory channels have independent command/address (CA) paths; and third and fourth memory channels having respective data widths, and configured to couple third and fourth I/O interfaces of the memory controller chiplet to an interface of the second memory device having a data channel width at least equal to the combined third and fourth memory channel widths, wherein the third and fourth memory channels have independent CA paths.

Abstract: A credit return field is used in a credit-based flow control system to indicate that one or more credits are being returned to a sending device from a receiving device. Based on the number of credits available, the sending device determines whether to send device or wait until more credits are returned. A write enable mask allows a wide data field to be used even when a smaller amount of data is to be written. A novel data packet uses a combined write enable mask and credit return field. In one mode, the field contains a write enable mask. In another mode, the field contains credit return data. If the field contains credit return data, a default value (e.g., all ones) is used for the write enable mask. The mode may be selected based on another value in the data packet.

Abstract: Devices and techniques for handling breakpoints in a multi-element processor are described herein. A compute node includes a hybrid threading processor and hybrid threading fabric, where the hybrid threading fabric comprises a plurality of memory-compute tiles, where each of the memory-compute tiles include respective processing and storage elements used to execute a kernel, and where each of the memory-compute tiles includes a breakpoint controller to initiate a breakpoint for the plurality of memory-compute tiles.

Abstract: Devices and techniques for loading contexts in a coarse-grained reconfigurable array processor are described herein. A system or apparatus may include context load circuitry operable to load context for a coarse-grained reconfigurable array processor, where the context load circuitry is configured to: (a) receive a kernel identifier; (b) access a first registry to obtain a context mask base address; (c) determine a context mask address from the context mask base address and the kernel identifier; (d) access a second registry to obtain a context state base address; (e) determine a context state address from the context state base address and the kernel identifier; (f) use a context mask at the context mask address to determine corresponding active context state; and (g) load the corresponding active context state into the coarse-grained reconfigurable array processor.

Abstract: Implementations of the present disclosure are directed to systems and methods for mapping point-to-point channels to packet virtual channels. A chip with an point-to-point interface converts point-to-point data to a packet format. The point-to-point channels are mapped to virtual channels of the packet transmission protocol. Information from multiple point-to-point channels may be combined in a single packet. Among the benefits of implementations of the present disclosure is that point-to-point devices may be connected to a packetized network without losing the benefits of separate channels for different types of communication. This allows existing point-to-point devices to communicate using a packetized network without internal modification or performance degradation.

Abstract: Implementations of the present disclosure are directed to systems and methods for processing headers that support multiple protocols. A header of a packet includes a bridge type (BTYPE) field that indicates the protocol of the packet. A command field of the packet is interpreted differently based on the value of the BTYPE field. Among the benefits of implementations of the present disclosure is that a single network may be used to carry packets of different protocols without the overhead of encapsulation.

Abstract: Devices and techniques for loading contexts in a coarse-grained reconfigurable array processor are described herein. A system or apparatus may include context load circuitry operable to load context for a coarse-grained reconfigurable array processor, where the context load circuitry is configured to: (a) receive a kernel identifier; (b) access a first registry to obtain a context mask base address; (c) determine a context mask address from the context mask base address and the kernel identifier; (d) access a second registry to obtain a context state base address; (e) determine a context state address from the context state base address and the kernel identifier; (f) use a context mask at the context mask address to determine corresponding active context state; and (g) load the corresponding active context state into the coarse-grained reconfigurable array processor.

Abstract: Devices and techniques for handling breakpoints in a multi-element processor are described herein. A compute node includes a hybrid threading processor and hybrid threading fabric, where the hybrid threading fabric comprises a plurality of memory-compute tiles, where each of the memory-compute tiles include respective processing and storage elements used to execute a kernel, and where each of the memory-compute tiles includes a breakpoint controller to initiate a breakpoint for the plurality of memory-compute tiles.

Abstract: A system may include multiple electronic devices and multiple hardware transceivers. The multiple electronic devices may be coupled to each other via an interface network, and may include multiple chiplets. The multiple hardware transceivers, with at least one transceiver included in or coupled to a respective electronic device of the multiple electronic devices, may each be configured to receive data packets from a source device. The data packets may each include a path field including path information indicating a path to a destination device and a bridge-type field including bridge-type information indicating a type of the path information in the path field. The source device and the destination device may each include a chiplet. The multiple hardware transceivers may each be further configured to transmit the received data packets to the destination device using the path information and the bridge-type information of each received data packet.

Abstract: Systems, apparatuses, and methods related to chiplets are described. A chiplet-based system may include a memory controller chiplet to control accesses to a storage array, and the memory controller chiplet can facilitate error correction and cache management in a manner to minimize interruptions to a sequence of data reads to write corrected data from a prior read back into the storage array. For example, a read command may be received at a memory controller device of the memory system from a requesting device. Data responsive to the read command may be obtained and determined to include a correctable error. The data may be corrected, transmitted to the requesting device and written to cache of the memory controller device with an indication that data is valid and dirty (e.g., includes an error or corrected error). The data is written back to the memory array in response to a cache eviction event.

Abstract: A chiplet system comprises an interposer including interconnect and multiple chiplets arranged on the interposer and interconnected using the interconnect of the interposer. The multiple chiplets include a throttle level bus source chiplet including a throttle level bus drive interface configured to place a throttle level value onto the throttle level bus, and one or more throttle level bus receiver chiplets operatively coupled to the throttle level bus. Each chiplet of the multiple chiplets includes throttling logic circuitry configured to set a throttle level of a chiplet according to the throttle level value.

Abstract: A system may include multiple electronic devices and multiple hardware transceivers. The multiple electronic devices may include multiple chiplets and may be coupled to each other via an interface network. The multiple hardware transceivers may each be included in or coupled to a respective electronic device of the multiple electronic devices. The multiple hardware transceivers may each be configured to receive data packets from a source device. The data packets each include a protocol field specifying ordering information for delivery to a destination device and a path field specifying path information for routing the delivery to the destination device. The source device and the destination device may each include a chiplet. The multiple hardware transceivers may each be further configured to transmit the received data packets to the destination device using at least the ordering information of each received data packet.

Abstract: Systems, apparatuses, and methods related to chiplets are described. A chiplet-based system may include a memory controller chiplet to control accesses to a storage array, and the memory controller chiplet can facilitate error correction and cache management in a manner to minimize interruptions to a sequence of data reads to write corrected data from a prior read back into the storage array. For example, a read command may be received at a memory controller device of the memory system from a requesting device. Data responsive to the read command may be obtained and determined to include a correctable error. The data may be corrected, transmitted to the requesting device and written to cache of the memory controller device with an indication that data is valid and dirty (e.g., includes an error or corrected error). The data is written back to the memory array in response to a cache eviction event.

Abstract: Implementations of the present disclosure are directed to systems and methods for processing headers that support multiple protocols. A header of a packet includes a bridge type (BTYPE) field that indicates the protocol of the packet. A command field of the packet is interpreted differently based on the value of the BTYPE field. Among the benefits of implementations of the present disclosure is that a single network may be used to carry packets of different protocols without the overhead of encapsulation.

Abstract: A system may include multiple electronic devices and multiple hardware transceivers. The multiple electronic devices may be coupled to each other via an interface network, and may include multiple chiplets. The multiple hardware transceivers, with at least one transceiver included in or coupled to a respective electronic device of the multiple electronic devices, may each be configured to receive data packets from a source device. The data packets may each include a path field including path information indicating a path to a destination device and a bridge-type field including bridge-type information indicating a type of the path information in the path field. The source device and the destination device may each include a chiplet. The multiple hardware transceivers may each be further configured to transmit the received data packets to the destination device using the path information and the bridge-type information of each received data packet.