Patents by Inventor David Patterson

David Patterson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10120892
    Abstract: Concepts and technologies are disclosed herein for providing and/or interacting with a profile verification service. A processor executing a profile verification service can receive a request to verify a user profile associated with a user of a social networking application. The processor can identify a computing device associated with the user profile, obtain location data that relates to the user profile and the computing device, and identify an activity associated with the computing device based upon the location data. The processor can determine if the user profile is accurate based upon the activity identified. If a determination is made that the user profile is accurate, the processor can verify the user profile. If a determination is made that the user profile is not accurate, the processor can update the user profile.
    Type: Grant
    Filed: August 12, 2014
    Date of Patent: November 6, 2018
    Assignees: AT&T Intellectual Property I, L.P., AT&T Mobility II LLC
    Inventors: David Patterson, Jeremy Fix, Sheldon Kent Meredith
  • Patent number: 10122007
    Abstract: A cover assembly for a battery module is configured to be coupled to battery cells that are arranged side-by-side in a stacked configuration. The cover assembly includes a housing, a plurality of bus bars, and an electrical cable. The bus bars are held by the housing and are configured to electrically connect to corresponding positive and negative cell terminals of the battery cells to electrically connect adjacent battery cells. The cable extends across the bus bars and is electrically connected to each of the bus bars to monitor voltages across the battery cells. The cable includes plural electrical conductors and a dielectric insulator that surrounds and electrically isolates the conductors. The conductors include exposed segments exposed through the dielectric insulator that are electrically connected to corresponding bus bars via a bonding layer applied between the exposed segment and the corresponding bus bar.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: November 6, 2018
    Assignee: TE CONNECTIVITY CORPORATION
    Inventors: David James Rhein, Andre Guanco, Eric Shields, Jeremy Patterson, Scott Cross
  • Patent number: 10108414
    Abstract: At least one ALM artifact, indexed by a unified data store, that does not comply with at least one process convention can be identified. Responsive to identifying the ALM artifact, indexed by the unified data store, that does not comply with the process convention, a determination can be made by a process convention agent executed by a processor as to whether script code is available to update the ALM artifact to comply with the process convention. Responsive to the process convention agent determining that script code is available to update the ALM artifact to comply with the process convention, the process convention agent can automatically execute the script code to update the ALM artifact to comply with the process convention.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: October 23, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Muhtar B. Akbulut, Mark T. Buquor, Vivek Garg, Matthew P. Jarvis, David Liman, Nimit Patel, Scott Patterson, Richard Watts, Keith A. Wells
  • Patent number: 10095479
    Abstract: A method is described that includes instantiating, within an application software development environment, a virtual processor having an instruction set architecture and memory model that contemplate first and second regions of reserved memory. The first reserved region is to keep data of an input image array. The second reserved region is to keep data of an output image array. The method also includes simulating execution of a memory load instruction of the instruction set architecture by automatically targeting the first reserved region and identifying desired input data with first and second coordinates relative to the virtual processor's position within an orthogonal coordinate system and expressed in the instruction format of the memory load instruction.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: October 9, 2018
    Assignee: Google LLC
    Inventors: Albert Meixner, Ofer Shacham, David Patterson, Daniel Frederic Finchelstein, Qiuling Zhu, Jason Rupert Redgrave
  • Patent number: 10096045
    Abstract: The present disclosure extends to methods, systems, and computer program products for providing item reviews to an online customer from third party sources during a shopping session on a retail website.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: October 9, 2018
    Assignee: WALMART APOLLO, LLC
    Inventors: David Stephen Bash, David Patterson
  • Patent number: 10091021
    Abstract: A portable acoustic unit is adapted for insertion into an electrical receptacle. The portable acoustic unit has an integrated microphone and a wireless network interface to an automation controller. The portable acoustic unit detects spoken voice commands from users in the vicinity of the electrical receptacle. The portable acoustic unit merely plugs into a conventional electrical outlet to provide an extremely simple means of voice control through a home or business.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: October 2, 2018
    Assignee: AT&T INTELLECTUAL PROPERTY I, L.P.
    Inventors: Nafiz Haider, Ross Newman, Kristin Patterson, Thomas Risley, Curtis Stephenson, David Vaught
  • Publication number: 20180275057
    Abstract: A method of making measurements includes providing a sensor with at least one solid state electronic spin; irradiating the sensor with radiation from an electromagnetic radiation source that manipulates the solid state electronic spins to produce spin-dependent fluorescence, wherein the spin-dependent fluorescence decays as a function of relaxation time; providing a target material in the proximity of the sensor, wherein, thermally induced currents (Johnson noise) present in the target material alters the fluorescence decay of the solid state electronic spins as a function of relaxation time; and determining a difference in the solid state spins spin-dependent fluorescence decay in the presence and absence of the target material and correlating the difference with a property of the sensor and/or target material.
    Type: Application
    Filed: January 29, 2016
    Publication date: September 27, 2018
    Inventors: Shimon Jacob KOLKOWITZ, Arthur SAFIRA, Alexander A. HIGH, Robert C. DEVLIN, Soonwon CHOI, Quirin P. UNTERREITHMEIER, David PATTERSON, Alexander S. ZIBROV, Vladimir E. MANUCHARYAN, Mikhail D. LUKIN, Hongkun PARK
  • Patent number: 10054686
    Abstract: The disclosed technology relates to systems and methods for managing one or more ground stations that track satellites. A non-transitory computer-readable storage medium stores information of a ground station at a first position at a first time. A processor receives from a sensor information of the ground station at a second position at a second time. The processor detects an anomaly of a positional characteristic of the ground station based on a difference between the first position and the second position. The processor outputs an instruction to calibrate the ground station based on the detected anomaly.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: August 21, 2018
    Assignee: SPIRE GLOBAL, INC.
    Inventors: Roshan Jobanputra, Jesse Trutna, David Patterson
  • Publication number: 20180234653
    Abstract: A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly shifting first content of multiple rows or columns of the two dimensional shift register array and repeatedly executing at least one instruction between shifts that operates on the shifted first content and/or second content that is resident in respective locations of the two dimensional shift register array that the shifted first content has been shifted into.
    Type: Application
    Filed: April 5, 2018
    Publication date: August 16, 2018
    Inventors: Albert Meixner, Daniel Frederic Finchelstein, David Patterson, William R. Mark, Jason Rupert Redgrave, Ofer Shacham
  • Patent number: 9986187
    Abstract: A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly shifting first content of multiple rows or columns of the two dimensional shift register array and repeatedly executing at least one instruction between shifts that operates on the shifted first content and/or second content that is resident in respective locations of the two dimensional shift register array that the shifted first content has been shifted into.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: May 29, 2018
    Assignee: Google LLC
    Inventors: Albert Meixner, Daniel Frederic Finchelstein, David Patterson, William R. Mark, Jason Rupert Redgrave, Ofer Shacham
  • Patent number: 9978116
    Abstract: A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, doubling a simultaneous shift amount of multiple rows or columns of the two dimensional shift register array with each next iteration. The method also includes executing one or more instructions within respective lanes of the two dimensional execution lane array in between shifts of iterations. Another method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly executing one or more instructions within respective lanes of the execution lane array that select between content in different registers of a same array location in between repeated simultaneous shifts of multiple rows or columns of data in the two dimensional shift register array.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: May 22, 2018
    Assignee: Google LLC
    Inventors: Albert Meixner, Daniel Frederic Finchelstein, David Patterson, William Mark, Jason Rupert Redgrave, Ofer Shacham
  • Patent number: 9967364
    Abstract: Methods, computer-readable media and apparatuses for predicting an amount of network infrastructure needed for a new neighborhood are disclosed. A processor generates a plurality of different user profiles based upon demographic data of existing customers, historical utilization data and historical usage data, determines a demographic of a new neighborhood, correlates one of the plurality of different user profiles to the new neighborhood based upon the demographic of the new neighborhood and predicts the amount of network infrastructure to be deployed in the new neighborhood based upon the one of the plurality of different user profiles that is correlated to the demographic of the new neighborhood.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: May 8, 2018
    Assignees: AT&T Mobility II LLC, AT&T Intellectual Property I, L.P.
    Inventors: Jeremy Fix, Juliette Niebuhr Zerick, David Patterson
  • Patent number: 9965824
    Abstract: An apparatus is described. The apparatus includes an image processing unit. The image processing unit includes a network. The image processing unit includes a plurality of stencil processor circuits each comprising an array of execution unit lanes coupled to a two-dimensional shift register array structure to simultaneously process multiple overlapping stencils through execution of program code. The image processing unit includes a plurality of sheet generators respectively coupled between the plurality of stencil processors and the network. The sheet generators are to parse input line groups of image data into input sheets of image data for processing by the stencil processors, and, to form output line groups of image data from output sheets of image data received from the stencil processors.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: May 8, 2018
    Assignee: Google LLC
    Inventors: Qiuling Zhu, Ofer Shacham, Albert Meixner, Jason Rupert Redgrave, Daniel Frederic Finchelstein, David Patterson, Neeti Desai, Donald Stark, Edward T. Chang, William R. Mark
  • Publication number: 20180082329
    Abstract: An online system allows a user to visualize a plan including various campaigns each including one or more content items associated with various objectives. Based on the plan, the online system provides forms or prompts for specifying characteristics, such as bid amounts or budgets, of content items. The online system may generate the plan based on one or more existing campaigns including various content items and characteristics for presenting content items in the existing campaign, allowing the user to identify differences between the plan and content items included in the existing campaigns. When content items included in the plan are included in selection processes by the online system, the online system obtains information describing presentation of content items from various campaigns included in the plan and aggregates the obtained information to provide information describing presentation of content items in the plan.
    Type: Application
    Filed: September 16, 2016
    Publication date: March 22, 2018
    Inventors: Kyle Edward Johnson, Charles David Patterson, Mairin Gates Wilson
  • Publication number: 20180007303
    Abstract: A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly shifting first content of multiple rows or columns of the two dimensional shift register array and repeatedly executing at least one instruction between shifts that operates on the shifted first content and/or second content that is resident in respective locations of the two dimensional shift register array that the shifted first content has been shifted into.
    Type: Application
    Filed: June 20, 2017
    Publication date: January 4, 2018
    Inventors: Albert Meixner, Daniel Frederic Finchelstein, David Patterson, William R. Mark, Jason Rupert Redgrave, Ofer Shacham
  • Publication number: 20180005075
    Abstract: A method is described that includes executing a convolutional neural network layer on an image processor having an array of execution lanes and a two-dimensional shift register. The executing of the convolutional neural network includes loading a plane of image data of a three-dimensional block of image data into the two-dimensional shift register.
    Type: Application
    Filed: June 23, 2017
    Publication date: January 4, 2018
    Inventors: Ofer Shacham, David Patterson, William R. Mark, Albert Meixner, Daniel Frederic Finchelstein, Jason Rupert Redgrave
  • Publication number: 20180005346
    Abstract: A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, doubling a simultaneous shift amount of multiple rows or columns of the two dimensional shift register array with each next iteration. The method also includes executing one or more instructions within respective lanes of the two dimensional execution lane array in between shifts of iterations. Another method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly executing one or more instructions within respective lanes of the execution lane array that select between content in different registers of a same array location in between repeated simultaneous shifts of multiple rows or columns of data in the two dimensional shift register array.
    Type: Application
    Filed: July 1, 2016
    Publication date: January 4, 2018
    Inventors: Albert MEIXNER, Daniel Frederic FINCHELSTEIN, David PATTERSON, William R. MARK, Jason Rupert REDGRAVE, Ofer SHACHAM
  • Publication number: 20180005347
    Abstract: A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, doubling a simultaneous shift amount of multiple rows or columns of the two dimensional shift register array with each next iteration. The method also includes executing one or more instructions within respective lanes of the two dimensional execution lane array in between shifts of iterations. Another method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly executing one or more instructions within respective lanes of the execution lane array that select between content in different registers of a same array location in between repeated simultaneous shifts of multiple rows or columns of data in the two dimensional shift register array.
    Type: Application
    Filed: May 17, 2017
    Publication date: January 4, 2018
    Applicant: Google Inc.
    Inventors: Albert Meixner, Daniel Frederic Finchelstein, David Patterson, William Mark, Jason Rupert Redgrave, Ofer Shacham
  • Publication number: 20180007302
    Abstract: A method is described that includes, on an image processor having a two dimensional execution lane array and a two dimensional shift register array, repeatedly shifting first content of multiple rows or columns of the two dimensional shift register array and repeatedly executing at least one instruction between shifts that operates on the shifted first content and/or second content that is resident in respective locations of the two dimensional shift register array that the shifted first content has been shifted into.
    Type: Application
    Filed: July 1, 2016
    Publication date: January 4, 2018
    Inventors: Albert MEIXNER, Daniel Frederic FINCHELSTEIN, David PATTERSON, William R. MARK, Jason Rupert REDGRAVE, Ofer SHACHAM
  • Publication number: 20180005074
    Abstract: A method is described that includes executing a convolutional neural network layer on an image processor having an array of execution lanes and a two-dimensional shift register. The two-dimensional shift register provides local respective register space for the execution lanes. The executing of the convolutional neural network includes loading a plane of image data of a three-dimensional block of image data into the two-dimensional shift register.
    Type: Application
    Filed: July 1, 2016
    Publication date: January 4, 2018
    Inventors: Ofer SHACHAM, David PATTERSON, William R. MARK, Albert MEIXNER, Daniel Frederic FINCHELSTEIN, Jason Rupert REDGRAVE