Patents by Inventor David Paul SINGLETON

David Paul SINGLETON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210064979
    Abstract: This application relates to computing circuitry (200, 500, 600) for analogue computing. A plurality of current generators (201) are each configured to generate a defined current (ID1, ID2, . . . IDj) based on a respective input data value (D1, D2, . . . Dj). A memory array (202), having at least one set (204) of programmable-resistance memory cells (203), is arranged to receive the defined currents from each of the current generators at a respective signal line (206). Each set (204) of programmable-resistance memory cells (203) includes a memory cell associated with each signal line that, in use, can be connected between the relevant signal line and a reference voltage so as to generate a voltage on the signal line. An adder module (207) is coupled to each of the signal lines to generate a voltage at an output node (210) based on the sum of the voltages on each of the signal lines.
    Type: Application
    Filed: August 29, 2019
    Publication date: March 4, 2021
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: Toru IDO, David Paul SINGLETON, Gordon James BATES, John Anthony BRESLIN
  • Patent number: 10298247
    Abstract: This application relates to analog-to-digital converter (ADC) circuitry (200). A time-encoding modulator (TEM 201) has a comparator (104) and a loop filter (105) configured to generate a pulse-width-modulated (PWM) signal (SPWM) in response to an input signal (SIN) and a feedback signal (SFB). A controlled oscillator, such as a VCO (202) receives the PWM signal and generates an output oscillation signal (SOSC) with a frequency that varies based on a drive signal at a drive node (109), e.g. a drive node of a ring oscillator (107). The controlled oscillator (202) comprises at least one control switch (112) controlled by a switch control signal (S1) generated from the received PWM signal so as to control the drive strength of the drive signal applied to the drive node (109). The feedback signal (SFB) for the TEM (201) is derived from the controlled oscillator (202) so as to include any timing error between the PWM signal and the switch control signal (S1) applied to said control switch.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: May 21, 2019
    Assignee: Cirrus Logic, Inc.
    Inventors: Louis Frew, Kapil Sharma, David Paul Singleton, Andrew James Howlett
  • Patent number: 10263633
    Abstract: This application relates time-encoding modulators such as may be used as part of analogue-to-digital conversion. A time-encoding modulator (100) receives an analogue input signal (SIN) at an input node (102) and outputs a corresponding time-encoded signal (SOUT) at an output node (103). A hysteretic comparator (101) has a first comparator input connected to the input node and a comparator output connected to the output node. A feedback path extends between the output node and a second comparator input of the hysteretic comparator; with a filter arrangement (104) arranged to apply filtering to the feedback path. The hysteretic comparator (101) compares the input signal (SIN) to the feedback signal (SFB) with hysteresis. This provides a pulse-width modulated output signal (SOUT) where the duty cycle encodes the input signal (SIN).
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: April 16, 2019
    Assignee: Cirrus Logic, Inc.
    Inventors: John Paul Lesso, David Paul Singleton
  • Patent number: 10254776
    Abstract: This application relates to methods and apparatus for voltage regulation. Embodiments relate to signal processing circuit (300) having a first and second processing path with respective first and second inputs (INP and INN). The first and second processing paths have respective first and second virtual earth nodes (108P and 108N) at the input to a differential integrator (106). A differential feedback path is configured to apply a feedback signal to each of the first and second virtual earth nodes so as to minimize any voltage difference between them. A regulator (301) is operable to monitor a voltage at one of the virtual earth nodes (108P) against a reference voltage (VREF) and to generate a regulation signal to maintain the voltage at said monitored one of the first and second virtual earth nodes to be equal to the reference voltage. The regulation signal is applied to both of the first and second virtual earth nodes.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: April 9, 2019
    Assignee: Cirrus Logic, Inc.
    Inventors: David Paul Singleton, Kapil Sharma
  • Publication number: 20180351569
    Abstract: This application relates time-encoding modulators such as may be used as part of analogue-to-digital conversion. A time-encoding modulator (100) receives an analogue input signal (SIN) at an input node (102) and outputs a corresponding time-encoded signal (SOUT) at an output node (103). A hysteretic comparator (101) has a first comparator input connected to the input node and a comparator output connected to the output node. A feedback path extends between the output node and a second comparator input of the hysteretic comparator; with a filter arrangement (104) arranged to apply filtering to the feedback path. The hysteretic comparator (101) compares the input signal (SIN) to the feedback signal (SFB) with hysteresis. This provides a pulse-width modulated output signal (SOUT) where the duty cycle encodes the input signal (SIN).
    Type: Application
    Filed: May 29, 2018
    Publication date: December 6, 2018
    Applicant: Cirrus Logic International Semiconductor Ltd.
    Inventors: John Paul LESSO, David Paul SINGLETON