Patents by Inventor David Paul Sonnier

David Paul Sonnier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Self-checked, lock step processor pairs
    Patent number: 6233702
    Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system. Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets. CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: May 15, 2001
    Assignee: Compaq Computer Corporation
    Inventors: Robert W. Horst, David J. Garcia, William Patterson Bunton, William F. Bruckert, Daniel L. Fowler, Curtis Willard Jones, Jr., David Paul Sonnier, William Joel Watson, Frank A. Williams
  • Method of data communication flow control in a data processing system using busy/ready commands
    Patent number: 6157967
    Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets.CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.
    Type: Grant
    Filed: December 30, 1997
    Date of Patent: December 5, 2000
    Assignee: Tandem Computer Incorporated
    Inventors: Robert W. Horst, William Edward Baker, Linda Ellen Zalzala, William Patterson Bunton, Richard W. Cutts, Jr., David J. Garcia, John C. Krause, Stephen G. Low, David Paul Sonnier, William Joel Watson, Patracia L. Whiteside
  • Network message routing using routing table information and supplemental enable information for deadlock prevention
    Patent number: 5914953
    Abstract: A processing system includes multiple processor units and multiple input/output elements communicatively interconnected by a system area network having a plurality of multi-ported router elements. Communication between the system elements uses message packets that contain, among other things, destination information that identifies the intended recipient of the message packet. That destination information is used, at least in part, for routing message packets from a its source to its intended destination. Deadlocks are eliminated by providing each router with information as to which ports cannot be used for re-transmission of a message packet, depending upon which port is receiving that message packet.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: June 22, 1999
    Assignee: Tandem Computers, Inc.
    Inventors: John C. Krause, David J. Garcia, Robert W. Horst, Geoffrey I. Iswandhi, David Paul Sonnier, William Joel Watson, Linda Ellen Zalzala
  • Apparatus for detecting divergence between a pair of duplexed, synchronized processor elements
    Patent number: 5790776
    Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets.CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 4, 1998
    Assignee: Tandem Computers Incorporated
    Inventors: David Paul Sonnier, William Edward Baker, William Patterson Bunton, John C. Krause, Kenneth H. Porter, William Joel Watson, Linda Ellen Zalzala
  • Method of synchronizing a pair of central processor units for duplex, lock-step operation by copying data into a corresponding locations of another memory
    Patent number: 5751955
    Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets.CPUs and I/O devices may write to, or read from, memory of a CPU of the system. Memory protection is provided by an access validation method maintained by each CPU in which CPUs and/or I/O devices are provided with a validation to read/write memory of that CPU, without which memory access is denied.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: May 12, 1998
    Assignee: Tandem Computers Incorporated
    Inventors: David Paul Sonnier, William Edward Baker, William Patterson Bunton, Daniel L. Fowler, Curtis Willard Jones, Jr., John C. Krause, Michael P. Simpson, William Joel Watson
  • Method for verifying responses to messages using a barrier message
    Patent number: 5675579
    Abstract: A processing system includes a number of communicatively interconnected system elements structured to send and receive data in the form of message packets. Message packets sent to a destination with expectation of response are timed, and if no response is received within an allotted time, a barrier transaction message packet is sent to the destination. The destination is required to provide a barrier transaction response to the barrier transaction packet only after it has responded to, or discarded, all prior received message packets requiring response by the destination. When the source of the barrier transaction message packet receives the barrier transaction response it can be assured that the communication path to the destination is in order, and no prior (late) responses will be forthcoming.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: October 7, 1997
    Assignee: Tandem Computers Incorporated
    Inventors: William Joel Watson, William Edward Baker, William F. Bruckert, William Patterson Bunton, David J. Garcia, Robert W. Horst, Geoffrey I. Iswandhi, David Joseph Kinkade, David Paul Sonnier
  • Interrupt message delivery identified by storage location of received interrupt data
    Patent number: 5675807
    Abstract: A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of the sub-processor systems may communicate, through the routing elements, with any I/O device of the system, or with any CPU of the system.Communications between I/O devices and CPUs is by packetized messages. Interrupts from I/O devices are communicated from the I/O devices to the CPUs (or from one CPU to another CPU) as message packets, and stored at an interrupt queue in memory. Storage of the interrupt data will initiate an internal interrupt to notify the receiving CPU. The receiving CPU can then access the interrupt queue, examine the interrupt data, and determine what action to take.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: October 7, 1997
    Assignee: Tandem Computers Incorporated
    Inventors: Geoffrey I. Iswandhi, William Edward Baker, William Patterson Bunton, John Deane Coddington, Daniel L. Fowler, David J. Garcia, Paul N. Hintikka, Susan Stone Meredith, Stephen H. Miller, David Paul Sonnier, William Joel Watson, Frank A. Williams