Patents by Inventor David Paulsen

David Paulsen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11120058
    Abstract: The present disclosure relates to systems, methods, and non-transitory computer readable media for generating and providing stacked attribution distributions within a stacked attribution user interface. For example, the disclosed systems can utilize attribution models to generate stacked attribution distributions as breakdowns of other attribution distributions. The disclosed systems can further provide a stacked attribution user interface that includes selectable elements for identifying event categories, dimensions, and attribution models for generating stacked attribution distributions. Based on user interaction with these selectable elements, the disclosed systems can dynamically generate, provide, and modify attribution breakdowns via the stacked attribution interface.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: September 14, 2021
    Assignee: Adobe Inc.
    Inventors: Trevor Paulsen, Nathan Purser, David Wilcox
  • Publication number: 20210279204
    Abstract: Verifying that data has been correctly replicated to a replication target, including: replicating a dataset stored at a first computing system to a second computing system; and determining, based at least on a comparison of a first hash and a second hash, validity of the dataset stored at the second computing system, wherein the first hash is generated by applying a hash function to a copy of the dataset that is stored at the first computing system and the second hash is generated by applying the hash function to a copy of the dataset that is stored at the second computing system.
    Type: Application
    Filed: May 17, 2021
    Publication date: September 9, 2021
    Inventors: DAVID GRUNWALD, LUKE PAULSEN, RONALD KARR, THOMAS GILL, YAO-CHENG TIEN
  • Publication number: 20210264543
    Abstract: Systems and methods for determining how to dispatch power to a property from a generator are provided. According to certain aspects, a controller associated with the generator may retrieve or access a set of data indicating time of use rates associated with utility power, performance characteristics of the generator, and/or energy usage data. Based on the data, the controller may determine a set point corresponding to when it may be beneficial to dispatch generator power to the property instead of utility power. At the set point, the controller may facilitate supplementing power from utility power with power from the generator. Additionally, the controller may collect usage and performance data associated with dispatch of the generator power.
    Type: Application
    Filed: February 24, 2020
    Publication date: August 26, 2021
    Inventors: David Walters, Richard Paulsen
  • Patent number: 10732931
    Abstract: A negative-operand compatible subtractor circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a difference output node to a voltage proportional to a difference between two received N-bit binary numbers. The subtractor circuit includes two sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The subtractor circuit includes two sets of scaled capacitors, each capacitor of two sets of scaled capacitors electrically connected to the difference output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The subtractor circuit includes a reset circuit configured to draw, in response to a received RESET signal, the difference output node to ground. A control circuit of the subtractor is configured to, in conjunction with the reset circuit, draw the difference output node to a reset voltage.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Phil Paone, David Paulsen, George Paulik, John E. Sheets, II, Karl Erickson, Gregory J. Uhlmann
  • Patent number: 10671348
    Abstract: A multiplier circuit can be fabricated within an integrated circuit and can draw a product output node to a voltage proportional to a product of first and second binary numbers received at two sets of inputs. The multiplier circuit includes a first set of scaled capacitors connected to an output of a multiplexor and to a local product output node. Each multiplexor is connected to a second set of scaled capacitors configured to generate an analog voltage in proportion to the value of the first binary number. Each scaled capacitor of first set of scaled capacitors has a capacitance proportional to a significance of a respective bit of the second binary number. The multiplier circuit includes a reference capacitor connected to ground and the product output node, and a reset circuit configured to draw, in response to a RESET signal, the product output node to ground.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: David Paulsen, Phil Paone, George Paulik, John E. Sheets, II, Karl Erickson
  • Publication number: 20200167126
    Abstract: A negative-operand compatible subtractor circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a difference output node to a voltage proportional to a difference between two received N-bit binary numbers. The subtractor circuit includes two sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The subtractor circuit includes two sets of scaled capacitors, each capacitor of two sets of scaled capacitors electrically connected to the difference output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The subtractor circuit includes a reset circuit configured to draw, in response to a received RESET signal, the difference output node to ground. A control circuit of the subtractor is configured to, in conjunction with the reset circuit, draw the difference output node to a reset voltage.
    Type: Application
    Filed: November 28, 2018
    Publication date: May 28, 2020
    Inventors: Phil Paone, David Paulsen, George Paulik, John E. Sheets, II, Karl Erickson, Gregory J. Uhlmann
  • Patent number: 10658993
    Abstract: A multiplier circuit can be fabricated within an integrated circuit and can draw a product output node to a voltage proportional to a product of first and second binary numbers received at two sets of inputs. The multiplier circuit includes a set of scaled capacitors, each capacitor of the set connected to an output of a multiplexor and to a local product output node. Each multiplexor is connected to the output of a multiplexor configured to generate an analog voltage in proportion to the value of the first binary number. Each scaled capacitor has a capacitance proportional to a significance of a respective bit of the second binary number. The multiplier circuit includes a reference capacitor connected to ground and the product output node, and a reset circuit configured to draw, in response to a RESET signal, the product output node to ground.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: David Paulsen, Phil Paone, George Paulik, John E. Sheets, II, Karl Erickson
  • Publication number: 20200125328
    Abstract: A multiplier circuit can be fabricated within an integrated circuit and can draw a product output node to a voltage proportional to a product of first and second binary numbers received at two sets of inputs. The multiplier circuit includes a first set of scaled capacitors connected to an output of a multiplexor and to a local product output node. Each multiplexor is connected to a second set of scaled capacitors configured to generate an analog voltage in proportion to the value of the first binary number. Each scaled capacitor of first set of scaled capacitors has a capacitance proportional to a significance of a respective bit of the second binary number. The multiplier circuit includes a reference capacitor connected to ground and the product output node, and a reset circuit configured to draw, in response to a RESET signal, the product output node to ground.
    Type: Application
    Filed: October 17, 2018
    Publication date: April 23, 2020
    Inventors: David Paulsen, Phil Paone, George Paulik, John E. Sheets, II, Karl Erickson
  • Publication number: 20200127626
    Abstract: A multiplier circuit can be fabricated within an integrated circuit and can draw a product output node to a voltage proportional to a product of first and second binary numbers received at two sets of inputs. The multiplier circuit includes a set of scaled capacitors, each capacitor of the set connected to an output of a multiplexor and to a local product output node. Each multiplexor is connected to the output of a multiplexor configured to generate an analog voltage in proportion to the value of the first binary number. Each scaled capacitor has a capacitance proportional to a significance of a respective bit of the second binary number. The multiplier circuit includes a reference capacitor connected to ground and the product output node, and a reset circuit configured to draw, in response to a RESET signal, the product output node to ground.
    Type: Application
    Filed: October 17, 2018
    Publication date: April 23, 2020
    Inventors: David Paulsen, Phil Paone, George Paulik, John E. Sheets, II, Karl Erickson
  • Patent number: 10592209
    Abstract: A multiplier circuit can be fabricated within an integrated circuit and can draw a product output node to a voltage proportional to a product of two received binary numbers. The multiplier circuit includes two sets of inputs that receive binary numbers. The multiplier circuit includes a set of scaled capacitors, each capacitor of the set connected to an output of an AND gate and to a local product output node. Each AND gate is connected to a unique pair of bits, one bit from each of the two binary numbers. Each scaled capacitor has a capacitance proportional to a product term generated by the corresponding AND gate. The multiplier circuit includes a reference capacitor connected to ground and the product output node, and a reset circuit configured to draw, in response to a RESET signal, the product output node to ground.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: March 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: David Paulsen, Phil Paone, George Paulik, John E. Sheets, II, Karl Erickson
  • Patent number: 10587282
    Abstract: An adder circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a sum output node to a voltage proportional to a sum of received N-bit binary numbers. The adder circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The adder circuit includes sets of scaled capacitors, each capacitor connected to an nth input of the corresponding set of N inputs and to the sum output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The adder circuit includes a reference capacitor connected to ground and the sum output node, and a reset circuit configured to draw, in response to a received RESET signal, the sum output node to ground.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: David Paulsen, Phil Paone, John E. Sheets, II, George Paulik, Karl Erickson, Gregory J. Uhlmann
  • Patent number: 10566987
    Abstract: A subtractor circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a difference output node to a voltage proportional to a difference between two received N-bit binary numbers. The subtractor circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The subtractor circuit includes two sets of scaled capacitors, each capacitor of one set connected to an nth input of the corresponding set of N inputs and to the difference output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The subtractor circuit includes a reference capacitor connected to ground and the difference output node, and a reset circuit configured to draw, in response to a received RESET signal, the difference output node to ground.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: February 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: David Paulsen, Phil Paone, John E. Sheets, II, George Paulik, Karl Erickson, Gregory J. Uhlmann
  • Publication number: 20190393886
    Abstract: A subtractor circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a difference output node to a voltage proportional to a difference between two received N-bit binary numbers. The subtractor circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The subtractor circuit includes two sets of scaled capacitors, each capacitor of one set connected to an nth input of the corresponding set of N inputs and to the difference output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The subtractor circuit includes a reference capacitor connected to ground and the difference output node, and a reset circuit configured to draw, in response to a received RESET signal, the difference output node to ground.
    Type: Application
    Filed: May 10, 2019
    Publication date: December 26, 2019
    Inventors: David Paulsen, Phil Paone, John E. Sheets, II, George Paulik, Karl Erickson, Gregory J. Uhlmann
  • Publication number: 20190393885
    Abstract: An adder circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a sum output node to a voltage proportional to a sum of received N-bit binary numbers. The adder circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The adder circuit includes sets of scaled capacitors, each capacitor connected to an nth input of the corresponding set of N inputs and to the sum output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The adder circuit includes a reference capacitor connected to ground and the sum output node, and a reset circuit configured to draw, in response to a received RESET signal, the sum output node to ground.
    Type: Application
    Filed: May 10, 2019
    Publication date: December 26, 2019
    Inventors: David Paulsen, Phil Paone, John E. Sheets, II, George Paulik, Karl Erickson, Gregory J. Uhlmann
  • Patent number: 10367520
    Abstract: A subtractor circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a difference output node to a voltage proportional to a difference between two received N-bit binary numbers. The subtractor circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The subtractor circuit includes two sets of scaled capacitors, each capacitor of one set connected to an nth input of the corresponding set of N inputs and to the difference output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The subtractor circuit includes a reference capacitor connected to ground and the difference output node, and a reset circuit configured to draw, in response to a received RESET signal, the difference output node to ground.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: July 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: David Paulsen, Phil Paone, John E. Sheets, II, George Paulik, Karl Erickson, Gregory J. Uhlmann
  • Patent number: 10348320
    Abstract: An adder circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a sum output node to a voltage proportional to a sum of received N-bit binary numbers. The adder circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The adder circuit includes sets of scaled capacitors, each capacitor connected to an nth input of the corresponding set of N inputs and to the sum output node. Each scaled capacitor has a capacitance equal to 2(n)* a unit capacitance (CUNIT). The adder circuit includes a reference capacitor connected to ground and the sum output node, and a reset circuit configured to draw, in response to a received RESET signal, the sum output node to ground.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: David Paulsen, Phil Paone, John E. Sheets, II, George Paulik, Karl Erickson, Gregory J. Uhlmann
  • Patent number: 9646298
    Abstract: Techniques for detecting the presence of a tag are described. According to one aspect of the present invention, a plurality of devices are deployed around an establishment, each of the devices is executing a client module to communicate with a server and receive a broadcast from a tag attached to an object (e.g., a human being or an item). As the object approaches to a device, the broadcast from the tag is received by a device that reports to the server. As a result, the server executing a server module can determine a movement trajectory of the object from those devices that have received the broadcast from the tag. One embodiment of the present invention can be used to track an asset or facilitate a location-based service to a user wearing the tag.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: May 9, 2017
    Assignee: Doorga Inc.
    Inventors: Charles Matthew Corbalis, Michael Edward Matthys, David Paulsen, Charles M. Robidart, Jr.
  • Publication number: 20160048878
    Abstract: Designs of a tag are described. Relevant parameters of the tag can be selected and determined via a device (e.g., a mobile device) running the client module in a predefined mode. Not only is the transmission power controlled to a small amount for detection of a nearby device, but the tag also operates periodically (e.g., every 2 or 10 seconds) to preserve the power driving it. The tag generates a transmission signal in compliance with a wireless technology standard so that the transmission signal can be received by a commonly-used device (e.g., a smartphone). In addition, for simplicity, the tag is not designed as a transceiver but operates as a transmitter only.
    Type: Application
    Filed: July 30, 2015
    Publication date: February 18, 2016
    Inventors: Charles Matthew Corbalis, Michael Edward Matthys, David Paulsen, Charles M. Robidart, JR.
  • Publication number: 20160050530
    Abstract: Techniques for detecting the presence of a tag are described. According to one aspect of the present invention, a plurality of devices are deployed around an establishment, each of the devices is executing a client module to communicate with a server and receive a broadcast from a tag attached to an object (e.g., a human being or an item). As the object approaches to a device, the broadcast from the tag is received by a device that reports to the server. As a result, the server executing a server module can determine a movement trajectory of the object from those devices that have received the broadcast from the tag. One embodiment of the present invention can be used to track an asset or facilitate a location-based service to a user wearing the tag.
    Type: Application
    Filed: July 30, 2015
    Publication date: February 18, 2016
    Inventors: Charles Matthew Corbalis, Michael Edward Matthys, David Paulsen, Charles M. Robidart, JR.
  • Publication number: 20160048827
    Abstract: Techniques for enabling micro-proximity location, detection and services are described. One embodiment of the present invention pertains to location and micro-proximity services technology in conjunction with fixed or mobile devices using a type of low energy signals (e.g., Bluetooth Low Energy (BLE) technology). With the detected location before a specific object, various proximity services may be customized with respect to the specific object.
    Type: Application
    Filed: July 30, 2015
    Publication date: February 18, 2016
    Inventors: Charles Matthew Corbalis, Michael Edward Matthys, David Paulsen, Charles M. Robidart, Jr.