Abstract: A method for depth mapping includes operating a projector at a first temperature to project a pattern of optical radiation onto a reference plane, capturing a first image of the projected pattern on the reference plane, using the first image and an optical and thermal model of the projector to compute multiple reference images associated with different respective temperatures of the projector. Using the projector, the pattern is projected onto a scene, and a temperature of the projector is measured while projecting the pattern. The method further includes capturing a second image of the projected pattern on the scene, selecting one of the reference images responsively to the measured temperature; and computing a depth map of the scene by comparing the pattern in the second image to the selected one of the reference images.

Abstract: A method for depth mapping includes providing a depth mapping device comprising a projector, which is configured to project a pattern of optical radiation onto a target area over a first field of view about a projection axis, and a camera, which is configured to capture images of the target area within a second field of view, narrower than the first field of view, about a camera axis, which is offset transversely relative to the projection axis. The projector projects the pattern onto first and second planes at first and second distances from the camera, and the camera captures first and second reference images containing first and second parts of the pattern on the first and second planes, respectively. The first and second reference images are combined to produce an extended reference image including both the first and second parts of the pattern.

Abstract: In one embodiment, a processor includes a plurality of intellectual property (IP) circuits, each to execute instructions and including a local control circuit to enable the IP circuit to operate at a level above a local current budget for the IP circuit, unless the processor is undergoing a global violation. The processor may further include a power controller coupled to the plurality of IP circuits. The power controller may include a control circuit to receive request information from the plurality of IP circuits and, based at least in part on the request information, determine that the processor is undergoing the global violation when a global current budget is exceeded. Other embodiments are described and claimed.

Abstract: One disclosed embodiment includes techniques for temperature-dependent reference image correction in structured light projectors that may be used for generating three-dimensional (3D) scene depth maps. The techniques disclosed herein include receiving an indication of a temperature (e.g., an actual current operating temperature or a change in the current operating temperature relative to an established reference temperature) associated with one or more components of a projector and then determining, based on the temperature indication, an amount of adjustment needed to correct a reference pattern image based on an estimated effective focal length change of the projector. Next, a reference pattern image may be appropriately adjusted, e.g.

Abstract: One disclosed embodiment includes techniques for temperature-dependent reference image correction in structured light projectors that may be used for generating three-dimensional (3D) scene depth maps. The techniques disclosed herein include receiving an indication of a temperature (e.g., an actual current operating temperature or a change in the current operating temperature relative to an established reference temperature) associated with one or more components of a projector and then determining, based on the temperature indication, an amount of adjustment needed to correct a reference pattern image based on an estimated effective focal length change of the projector. Next, a reference pattern image may be appropriately adjusted, e.g.

Abstract: In one embodiment, a processor includes a plurality of intellectual property (IP) circuits, each to execute instructions and including a local control circuit to enable the IP circuit to operate at a level above a local current budget for the IP circuit, unless the processor is undergoing a global violation. The processor may further include a power controller coupled to the plurality of IP circuits. The power controller may include a control circuit to receive request information from the plurality of IP circuits and, based at least in part on the request information, determine that the processor is undergoing the global violation when a global current budget is exceeded. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor includes a plurality of intellectual property (IP) circuits, each to execute instructions and including a local control circuit to enable the IP circuit to operate at a level above a local current budget for the IP circuit, unless the processor is undergoing a global violation. The processor may further include a power controller coupled to the plurality of IP circuits. The power controller may include a control circuit to receive request information from the plurality of IP circuits and, based at least in part on the request information, determine that the processor is undergoing the global violation when a global current budget is exceeded. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor includes a plurality of intellectual property (IP) circuits, each to execute instructions and including a local control circuit to enable the IP circuit to operate at a level above a local current budget for the IP circuit, unless the processor is undergoing a global violation. The processor may further include a power controller coupled to the plurality of IP circuits. The power controller may include a control circuit to receive request information from the plurality of IP circuits and, based at least in part on the request information, determine that the processor is undergoing the global violation when a global current budget is exceeded. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor includes a plurality of intellectual property (IP) circuits, each to execute instructions and including a local control circuit to enable the IP circuit to operate at a level above a local current budget for the IP circuit, unless the processor is undergoing a global violation. The processor may further include a power controller coupled to the plurality of IP circuits. The power controller may include a control circuit to receive request information from the plurality of IP circuits and, based at least in part on the request information, determine that the processor is undergoing the global violation when a global current budget is exceeded. Other embodiments are described and claimed.

Abstract: Compositions comprising a polyolefin polymer and an expanded graphite exhibit uniform conductivity over a broad range of temperature. In one embodiment, the polyolefin polymer is polypropylene or polyethylene homopolymer or a polypropylene or polyethylene copolymer. The compositions provide uniform conductivity and can be used as a conductive formulation for medium and high voltage cable components.

Abstract: Compositions comprising a polyolefin polymer and an expanded graphite exhibit uniform conductivity over a broad range of temperature. In one embodiment, the polyolefin polymer is polypropylene or polyethylene homopolymer or a polypropylene or polyethylene copolymer. The compositions provide uniform conductivity and can be used as a conductive formulation for medium and high voltage cable components.