Abstract: A CPU of a microprocessor includes a common bus, a bus interface unit (BIU), and a plurality of module units. The BIU has a plurality of first ports coupled to respective first ports of the module units via dedicated buses therebetween and has a second port coupled to a first port of the common bus. The module units each include a second port coupled to respective second ports of the common bus. Communication between the module units is routed through and controlled by the BIU. To request a transaction, a module unit (the initiator) sends a request to the BIU via its dedicated bus to the BIU. The BIU arbitrates among present requests and, in response thereto, grants the arbitration winner's request and transmits a command to the target of the requested transaction. Preferably, both of these signals being are transmitted via the dedicated buses. Thereafter, data is routed from, for instance, the target, to the BIU via a corresponding dedicated bus.

Abstract: A system for maintaining completion order in a multiple bus system including a bridge that posts write data includes logic units for implementing a DRAIN/EMPTY protocol. A bridge logic unit asserts an EMPTY signal when the secondary posting buffers are empty. Interrupt processing is delayed until the EMPTY signal is asserted thereby assuring that all writes are completed. If an interrupt is received and the EMPTY signal is not asserted then a DRAIN signal is asserted while the EMPTY signal is not asserted. The bridge retries all upstream write requests until EMPTY is asserted.