Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to determine memory access integrity based on feedback from memory. An example apparatus includes an access reconstruction controller including an output, a first input configured to be coupled to memory, and a second input configured to be coupled to a memory signal generator; a comparator including a first input coupled to the output of the access reconstruction controller, a second input configured to be coupled to an arbiter, and an output configured to be coupled to the arbiter; and a data integrity monitor including an input coupled to the second input of the comparator and configured to be coupled to the arbiter and an output coupled to the output of the comparator and configured to be coupled to the arbiter.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to determine memory access integrity based on feedback from memory. An example apparatus includes an access reconstruction controller including an output, a first input configured to be coupled to memory, and a second input configured to be coupled to a memory signal generator; a comparator including a first input coupled to the output of the access reconstruction controller, a second input configured to be coupled to an arbiter, and an output configured to be coupled to the arbiter; and a data integrity monitor including an input coupled to the second input of the comparator and configured to be coupled to the arbiter and an output coupled to the output of the comparator and configured to be coupled to the arbiter.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for safety mechanisms to actively detect address faults. An example system includes a first parity generator, a second parity generator, and a parity checker. The first parity generator is to generate a first parity based on a first address information. The first address information corresponds to a desired location to store data in a memory storage array. The second parity generator is to generate a second parity based on a second address information. The second address information corresponding to an actual location where the data is stored in the memory storage array. The parity checker is to compare the first parity and the second parity to detect a fault.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed for safety mechanisms to actively detect address faults. An example system includes a first parity generator, a second parity generator, and a parity checker. The first parity generator is to generate a first parity based on a first address information. The first address information corresponds to a desired location to store data in a memory storage array. The second parity generator is to generate a second parity based on a second address information. The second address information corresponding to an actual location where the data is stored in the memory storage array. The parity checker is to compare the first parity and the second parity to detect a fault.

Abstract: A system includes a central processing unit (CPU) core, and a pulse width modulator (PWM) controller configured to generate a PWM control signal having a PWM cycle. The system also includes an analog-to-digital converter (ADC), an accumulator, a sum register, and an oversampling register set. The oversampling register set is configurable by the CPU core to specify time points during each PWM cycle when the ADC is to convert an analog signal to a digital sample to produce a plurality of digital samples. The time spacing between consecutive digital samples varies among the specified time points. The accumulator accumulates digital samples from the ADC and stores an accumulated sum in the sum register. The CPU core reads the accumulated sum from the sum register, and can use the accumulated sum to calculate a metric (e.g., an average) of the digital samples.

Abstract: An integrated circuit (IC) chip and method of booting the IC are disclosed. The method includes determining whether a boot pin configuration has been programmed and responsive to determining that the boot pin configuration has been programmed, performing a boot method indicated in a user-defined boot table. Responsive to determining that the boot pin configuration key has not been programmed, the method performs a boot method selected from a factory-defined boot table.

Abstract: An integrated circuit (IC) chip and method of booting the IC are disclosed. The method includes determining whether a boot pin configuration has been programmed and responsive to determining that the boot pin configuration has been programmed, performing a boot method indicated in a user-defined boot table. Responsive to determining that the boot pin configuration key has not been programmed, the method performs a boot method selected from a factory-defined boot table.

Abstract: Multiple secure environments are established within a system on a chip (SoC) by defining a first secure region within a non-volatile memory in the SoC with a first set of parameters written into a predefined parameter region of the non-volatile memory. A second secure region within the non-volatile memory may be defined at a later time by a second set of parameters written into another predefined parameter region of the non-volatile memory. A security module is initialized each time the SoC is powered on by transferring the first set of parameters and the second set of parameters from the parameter region to the security module in a manner that does not expose the first set of parameters or the second set of parameters to a program being executed by the processor. The multiple secure regions of the SoC are enforced by the security module according to the parameter data.

Abstract: Multiple secure environments are established within a system on a chip (SoC) by defining a first secure region within a non-volatile memory in the SoC with a first set of parameters written into a predefined parameter region of the non-volatile memory. A second secure region within the non-volatile memory may be defined at a later time by a second set of parameters written into another predefined parameter region of the non-volatile memory. A security module is initialized each time the SoC is powered on by transferring the first set of parameters and the second set of parameters from the parameter region to the security module in a manner that does not expose the first set of parameters or the second set of parameters to a program being executed by the processor. The multiple secure regions of the SoC are enforced by the security module according to the parameter data.