Patents by Inventor David Peterson

David Peterson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9966308
    Abstract: A method of forming a semiconductor device includes forming a sacrificial layer in a first contact hole of a first dielectric layer, forming a second dielectric layer on the first dielectric layer, and forming a second contact hole in the second dielectric layer, the second contact hole being aligned with the first contact hole, removing the sacrificial layer from the first contact hole, forming a liner layer on the second dielectric layer and in the first and second contact holes, and forming a copper contact in the first and second contact holes.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: May 8, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Baozhen Li, Kirk David Peterson, John E. Sheets, II, Junli Wang, Chih-Chao Yang
  • Publication number: 20180122697
    Abstract: A method of forming a semiconductor device includes forming a sacrificial layer in a first contact hole of a first dielectric layer, forming a second dielectric layer on the first dielectric layer, and forming a second contact hole in the second dielectric layer, the second contact hole being aligned with the first contact hole, removing the sacrificial layer from the first contact hole, and forming a copper contact in the first and second contact holes.
    Type: Application
    Filed: December 29, 2017
    Publication date: May 3, 2018
    Inventors: Lawrence A. Clevenger, Baozhen Li, Kirk David Peterson, John E. Sheets, II, Junli Wang, Chih-Chao Yang
  • Patent number: 9941300
    Abstract: A method for fabricating a fully depleted silicon on insulator (FDSOI) device is described. A charge trapping layer in a buried oxide layer is provided on a semiconductor substrate. A backgate well in the semiconductor substrate is provided under the charge trapping layer. A device structure including a gate structure, source and drain regions is disposed over the buried oxide layer. A charge is trapped in the charge trapping layer. The threshold voltage of the device is partially established by the charge trapped in the charge trapping layer. Different aspects of the invention include the structure of the FDSOI device and a method of tuning the charge trapped in the charge trapping layer of the FDSOI device.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: April 10, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John Joseph Ellis-Monaghan, Terence B Hook, Kirk David Peterson
  • Publication number: 20180096890
    Abstract: A method of forming a semiconductor device includes forming a sacrificial layer in a first contact hole of a first dielectric layer, forming a second dielectric layer on the first dielectric layer, and forming a second contact hole in the second dielectric layer, the second contact hole being aligned with the first contact hole, removing the sacrificial layer from the first contact hole, forming a liner layer on the second dielectric layer and in the first and second contact holes, and forming a copper contact in the first and second contact holes.
    Type: Application
    Filed: October 4, 2016
    Publication date: April 5, 2018
    Inventors: Lawrence A. CLEVENGER, Baozhen LI, Kirk David Peterson, John E. SHEETS, II, Junli WANG, Chih-Chao YANG
  • Publication number: 20180062322
    Abstract: A conduit assembly with a tube formed from a polymeric material with a nanoparticulate component. The polymeric material has an electrical conductivity in a range between 1×10?14 and 4.7×106 (S/m) at 20° C. An electrical contact is electrically coupled with the conduit assembly to receive electrical current. A ground is electrically coupled with the conduit assembly to ground the electrical current passed through the conduit assembly.
    Type: Application
    Filed: August 29, 2017
    Publication date: March 1, 2018
    Inventors: Brant LYALL, David PETERSON, Brian IGNACZAK
  • Publication number: 20180006025
    Abstract: A semiconductor and a method of forming a semiconductor on a single chip, including forming a shallow trench isolation (STI) region on a short channel device and a long channel device, forming at least two vertical fins connected in the long channel device, and forming contacts on a source and drain regions for the long channel device and short channel device, wherein the contacts connect a top surface of the source or drain region for series FET (Field-Effect Transistor) connection for the long channel device.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 4, 2018
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Terence B. Hook, Baozhen Li, Kirk David Peterson, Junli Wang
  • Patent number: 9852073
    Abstract: In one embodiment, a computing system includes a cache and a cache manager. The cache manager is able to receive data, write the data to a first portion of the cache, write the data to a second portion of the cache, and delete the data from the second portion of the cache when the data in the first portion of the cache is flushed.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: December 26, 2017
    Assignee: DELL PRODUCTS L.P.
    Inventors: Scott David Peterson, Phillip E. Krueger
  • Patent number: 9853868
    Abstract: Cloud computing has emerged as an extremely popular implementation option for a wide range of computing services. However, provisioning services into the cloud is an extremely difficult technical challenge. This is due in part to the regular emergence of new cloud service providers, as well as the routine changing and reconfiguration of the disparate computing platforms, services, assets, supported technical components, and other features offered by the service providers. An analysis architecture determines how to map a particular technical component into the execution environment of any particular service provider.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: December 26, 2017
    Assignee: Accenture Global Services Limited
    Inventors: Patrick Francis Cimprich, Michael Gerald DeLuca, Jack Q. W. Cantwell, Sean David Peterson, Marshall J. Wells
  • Publication number: 20170365239
    Abstract: A practical solution to the problem of tension equalization in wire tensioned around drums and objects, wire end securing devices, and the protracted wire replacement and tensioning time. In some embodiments, jaws in cooperating chambers replace securing knots, which eliminates a sources of tension equalization, the protracted time in tying the knot, and thus permits rapid wire installation and automatic wire clamping. Some embodiments use linear translation via pistons to replace take-up drums, thereby eliminating another source of tension equalization. Other embodiments increase tension equalization by reducing the length of wire wrapped around drums or bridge tie-blocks. Yet other embodiments utilize drums having surfaces which reduce or increase tension equalization. Wire quick release mechanisms, rapid manual course tensioning, and compatibility with automated tensioning tools, address the protracted time in wire replacement and tensioning.
    Type: Application
    Filed: June 17, 2016
    Publication date: December 21, 2017
    Inventor: David A. Peterson
  • Publication number: 20170322882
    Abstract: A cache storage method includes providing a storage cache cluster, comprising a plurality of cache storage elements, for caching I/O operations from a plurality of virtual machines associated with a corresponding plurality of virtual hard disks mapped to a logical storage area network volume or LUN. Responsive to a cache flush signal, flush write back operations are performed to flush modified cache blocks to achieve or preserve coherency. The flush write back operations may include accessing current time data indicative of a current time, determining a current time window in accordance with the current time, determining a duration of the current time window, and identifying a current cache storage element corresponding to the current time window. For a duration of the current time window, only those write back blocks stored in the current cache storage element are flushed.
    Type: Application
    Filed: May 9, 2016
    Publication date: November 9, 2017
    Applicant: Dell Products L.P.
    Inventors: Scott David PETERSON, Sujoy SEN
  • Patent number: 9749195
    Abstract: Determining placement options for technical components of a specified service is a difficult technical challenge. A metadata architecture addresses, in part, the technical challenge by defining a complex metadata collection and attachment mechanism. In one implementation, the metadata architecture defines metadata domains and obtains descriptive metadata for those domains, e.g., metadata for the technical components from multiple disparate sources and across multiple different characteristics of the technical components. The metadata architecture is linked to the technical components and the metadata architecture injects specific metadata subsets into, e.g., a placement pipeline that determines where the technical components may be placed in the extensive provider/platform/service space.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: August 29, 2017
    Assignee: Accenture Global Services Limited
    Inventors: Patrick Francis Cimprich, Michael Gerald DeLuca, Jack Q. W. Cantwell, Sean David Peterson, Marshall J. Wells
  • Publication number: 20170216151
    Abstract: A package for consuming a food product in a frozen or non-frozen state. The package includes a pouch body and a fitment. The pouch body defines a chamber for receiving the food product and includes a cut of predetermined depth to facilitate tearing of the pouch body to create an opening for dispensing the food product in a frozen state. The fitment includes a spout for dispensing the food product in a non-frozen state.
    Type: Application
    Filed: February 1, 2017
    Publication date: August 3, 2017
    Inventors: Joel Dean GENAW, JR., Matthew Blake RODGERS, Barbara Burzinski HARTLIEP, Scott David PETERSON
  • Publication number: 20170217641
    Abstract: A flexible pouch has an internal zipper adding support to the pouch and allowing the contents of the pouch to be portioned. Flexible pouches having a product disposed therein are also disclosed, along with kits containing same. In addition, methods of producing the flexible pouches and packaged products are also disclosed.
    Type: Application
    Filed: February 1, 2017
    Publication date: August 3, 2017
    Inventors: Joel Dean GENAW, JR., Matthew Blake RODGERS, Barbara Burzinski HARTLIEP, Scott David PETERSON
  • Patent number: 9702668
    Abstract: Linear shaped charges are described herein. In a general embodiment, the linear shaped charge has an explosive with an elongated arrowhead-shaped profile. The linear shaped charge also has and an elongated v-shaped liner that is inset into a recess of the explosive. Another linear shaped charge includes an explosive that is shaped as a star-shaped prism. Liners are inset into crevices of the explosive, where the explosive acts as a tamper.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: July 11, 2017
    Assignee: National Technology & Engineering Solutions of Sandia, LLC
    Inventors: David Peterson, Jerome H. Stofleth, W. Venner Saul
  • Publication number: 20170190650
    Abstract: A process for removing acetic acid from an aqueous stream containing yellow oil. According to the process, yellow oil is removed from the aqueous stream prior to the removal of acetic acid by a reverse osmosis membrane.
    Type: Application
    Filed: December 29, 2016
    Publication date: July 6, 2017
    Applicant: BP Corporation North America Inc.
    Inventors: DAVID PETERSON, Sameer Talreja
  • Publication number: 20170179156
    Abstract: A method for fabricating a fully depleted silicon on insulator (FDSOI) device is described. A charge trapping layer in a buried oxide layer is provided on a semiconductor substrate. A backgate well in the semiconductor substrate is provided under the charge trapping layer. A device structure including a gate structure, source and drain regions is disposed over the buried oxide layer. A charge is trapped in the charge trapping layer. The threshold voltage of the device is partially established by the charge trapped in the charge trapping layer. Different aspects of the invention include the structure of the FDSOI device and a method of tuning the charge trapped in the charge trapping layer of the FDSOI device.
    Type: Application
    Filed: December 16, 2015
    Publication date: June 22, 2017
    Inventors: John Joseph Ellis-Monaghan, Terence B. Hook, Kirk David Peterson
  • Publication number: 20170149924
    Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor and a memory communicatively coupled to the processor, the memory for storing a portion of a cache. The memory may be configured to receive a request to write data to the portion of the cache, write the data to the portion of the cache, and update a map corresponding to the cache and stored within the memory.
    Type: Application
    Filed: November 19, 2015
    Publication date: May 25, 2017
    Applicant: Dell Products L.P.
    Inventors: Scott David Peterson, Sujoy Sen
  • Patent number: 9632835
    Abstract: A resource management node includes a processor and a memory coupled to the processor. The memory includes computer readable program code that when executed by the processor causes the processor to perform operations. The operations can include, for each of a plurality of guest virtual machines (VMs), determining operational resources of physical host machines available in a distributed computing system that are needed to provide the guest VM. A placement scenario for placing the guest VMs on the physical host machines and placing the physical host machines in cabinets of a distributed computing system is generated. An amount of infrastructure of the distributed computing system used by the placement scenario is determined. A determination is made whether the placement scenario satisfies a defined rule for how much infrastructure of the distributed computing system can be used.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: April 25, 2017
    Assignee: CA, Inc.
    Inventors: Lara Virginia Greden, Peter James Gilbert, Richard John Wcislicki Lankester, James B. Mercer, John Wiley Ashby, Jr., Salvatore Pilo, Paul David Peterson, Francois Marie Bruno Cattoen
  • Publication number: 20170078161
    Abstract: Cloud computing has emerged as an extremely popular implementation option for a wide range of computing services. However, provisioning services into the cloud is an extremely difficult technical challenge. This is due in part to the regular emergence of new cloud service providers, as well as the routine changing and reconfiguration of the disparate computing platforms, services, assets, supported technical components, and other features offered by the service providers. An analysis architecture determines how to map a particular technical component into the execution environment of any particular service provider with the aid of translation scripts.
    Type: Application
    Filed: November 4, 2016
    Publication date: March 16, 2017
    Inventors: Patrick Francis Cimprich, Michael Gerald DeLuca, Jack Q.W. Cantwell, Sean David Peterson, Marshall J. Wells
  • Publication number: 20170078162
    Abstract: Cloud computing has emerged as an extremely popular implementation option for a wide range of computing services. However, provisioning services into the cloud is an extremely difficult technical challenge. This is due in part to the regular emergence of new cloud service providers, as well as the routine changing and reconfiguration of the disparate computing platforms, services, assets, supported technical components, and other features offered by the service providers. An analysis architecture determines how to map a particular technical component into the execution environment of any particular service provider, including translation through a reference type.
    Type: Application
    Filed: November 4, 2016
    Publication date: March 16, 2017
    Inventors: Patrick Francis Cimprich, Michael Gerald DeLuca, Jack Q.W. Cantwell, Sean David Peterson, Marshall J. Wells