Abstract: A mechanism is provided by which a hardware accelerator detects migration of a software process among processors and uses this information to write operation results to an appropriate cache memory for faster access by the current processor. This mechanism is provided, in part, by incorporation within the hardware accelerator of a mapping table having entries including a cache memory identifier associated with a processor identifier. The hardware accelerator further includes circuitry configured to receive a processor identifier from a calling processor, and to perform a look-up in the mapping table to determine the cache memory identifier associated with the processor identifier. The hardware accelerator uses the associated cache memory identifier to write results of called operations to the cache memory associated with the calling processor, thereby accelerating subsequent operations by the calling processor that rely upon the hardware accelerator results.

Abstract: A mechanism is provided by which a hardware accelerator detects migration of a software process among processors and uses this information to write operation results to an appropriate cache memory for faster access by the current processor. This mechanism is provided, in part, by incorporation within the hardware accelerator of a mapping table having entries including a cache memory identifier associated with a processor identifier. The hardware accelerator further includes circuitry configured to receive a processor identifier from a calling processor, and to perform a look-up in the mapping table to determine the cache memory identifier associated with the processor identifier. The hardware accelerator uses the associated cache memory identifier to write results of called operations to the cache memory associated with the calling processor, thereby accelerating subsequent operations by the calling processor that rely upon the hardware accelerator results.

Abstract: A hash accelerator is provided that receives a hash key value from a processor core, determines a main memory address storing a hash table entry corresponding to the hash key value, and causes the hash table entry to be stored in a cache memory accessible by the processor core. The hash accelerator is configured to execute the same hash function that the processor core executes, and if the hash accelerator is faster than the software executing on the processor core, the hash table entry can be available to the core processor from cache memory by the time the processor core attempts to access the entry. This avoids a cache miss by the processor core, thereby improving overall efficiency of routines executed by the processor core.

Abstract: A hash accelerator is provided that receives a hash key value from a processor core, determines a main memory address storing a hash table entry corresponding to the hash key value, and causes the hash table entry to be stored in a cache memory accessible by the processor core. The hash accelerator is configured to execute the same hash function that the processor core executes, and if the hash accelerator is faster than the software executing on the processor core, the hash table entry can be available to the core processor from cache memory by the time the processor core attempts to access the entry. This avoids a cache miss by the processor core, thereby improving overall efficiency of routines executed by the processor core.

Abstract: Systems, devices, and methods relating to network firewalls and VPN gateways for controlling and securing access to networks. An integrated VPN/firewall system comprises at least one policy engine module, a switch module, a cryptographic engine module, and at least one flow engine module. Each flow engine module receives DTUs from either side of the integrated VPN/firewall system. The DTUs are then compared to entries in a listening table and entries in a flow table. The entries in these tables consist of characteristics of DTUs expected to arrive for specific flows. Entries to both listening tables and flow tables are made by the policy engine with listening table entries generally denoting flows potentially allowed by policy to be established between computers on opposite sides of the system. Flow tables, on the other hand, correspond to flows already allowed to be established between computers on opposite sides of the firewall system.

Abstract: Systems, devices, and methods relating to network firewalls and VPN gateways for controlling and securing access to networks. An integrated VPN/firewall system comprises at least one policy engine module, a switch module, a cryptographic engine module, and at least one flow engine module. Each flow engine module receives DTUs from either side of the integrated VPN/firewall system. The DTUs are then compared to entries in a listening table and entries in a flow table. The entries in these tables consist of characteristics of DTUs expected to arrive for specific flows. If a DTU matches an entry, the DTU may be forwarded by the ingress flow engine to the egress flow engine via the switch module, and subsequently to its destination by the egress flow engine; or it may be forwarded, using the switch module, to the policy engine module for further security checking, or to the cryptographic engine module for encryption/decryption required for VPN operations.