Abstract: A memory device. The memory device includes an array of word lines and complementary bit line pairs. A number of memory cells are each addressably coupled to intersections of the word line with a bit line of a complementary bit line pair. The memory device also includes addressing circuitry that is coupled to the array so as to select a memory cell. Further, a number of sense amplifiers are provided. Each sense amplifier is coupled to a complementary pair of bit lines. Each complementary pair of bit lines is also coupled to an equilibration circuit. A transistor controllably couples the reference voltage source to the equilibration circuit The transistor is disabled when one of the bit lines of the complementary pair is defective so as to isolate the reference voltage source and prevent leakage current.

Abstract: A memory device. The memory device includes an array of word lines and complementary bit line pairs. A number of memory cells are each addressably coupled to intersections of the word line with a bit line of a complementary bit line pair. The memory device also includes addressing circuitry that is coupled to the array so as to select a memory cell. Further, a number of sense amplifiers are provided. Each sense amplifier is coupled to a complementary pair of bit lines. Each complementary pair of bit lines is also coupled to an equilibration circuit. A transistor controllably couples the reference voltage source to the equilibration circuit. The transistor is disabled when one of the bit lines of the complementary pair is defective so as to isolate the reference voltage source and prevent leakage current.

Abstract: A memory device. The memory device includes an array of word lines and complementary bit line pairs. A number of memory cells are each addressably coupled to intersections of the word line with a bit line of a complementary bit line pair. The memory device also includes addressing circuitry that is coupled to the array so as to select a memory cell. Further, a number of sense amplifiers are provided. Each sense amplifier is coupled to a complementary pair of bit lines. Each complementary pair of bit lines is also coupled to an equilibration circuit. A transistor controllably couples the reference voltage source to the equilibration circuit. The transistor is disabled when one of the bit lines of the complementary pair is defective so as to isolate the reference voltage source and prevent leakage current.

Abstract: A memory device. The memory device includes an array of word lines and complementary bit line pairs. A number of memory cells are each addressably coupled to intersections of the word line with a bit line of a complementary bit line pair. The memory device also includes addressing circuitry that is coupled to the array so as to select a memory cell. Further, a number of sense amplifiers are provided. Each sense amplifier is coupled to a complementary pair of bit lines. Each complementary pair of bit lines is also coupled to an equilibration circuit. A transistor controllably couples the reference voltage source to the equilibration circuit. The transistor is disabled when one of the bit lines of the complementary pair is defective so as to isolate the reference voltage source and prevent leakage current.

Abstract: A CMOS integrated circuit output terminal driver subcircuit (60) provides quick response at an output terminal (56) of an integrated circuit (50) while preventing reverse current leakage when an external high voltage, which exceeds the positive internal circuit source voltage of the integrated circuit, is imposed on the output terminal (56). The output driver subcircuit (60) additionally provides an output voltage at the output terminal that is only nominally below the internal circuit source voltage. A p-channel MOS pull-up transistor (62) is operably connected to the output terminal (56) to selectively drive it substantially to the internal circuit source voltage. A leakage prevention device (66), comprising a native n-channel transistor (68) with a low turn-on threshold voltage, is connected in series with the pull-up transistor (62) to prevent output terminal reverse current leakage back through the pull-up transistor (62) when the external high voltage is imposed upon the output terminal (56).