Abstract: Method and apparatus for content protection using one-way buffers. In one embodiment, the method includes storage of content decrypted by a host processor within a reserved range of memory. In one embodiment, a peripheral device requires the host processor to decrypt the received content for playback by the peripheral device. The decrypted content is stored within a reserved range of memory that is not accessible by malicious software. Hence, content is transferred from the reserved range of memory to a device driver of the peripheral device. In one embodiment, access to the reserved range of memory consists of write-only access by the host processor and read-only access by the peripheral device. In one embodiment, prior to storage of the content within the reserved range of memory, the content is re-encrypted prior to storage and decryption prior to transfer to the peripheral device. Other embodiments are described and claimed.

Abstract: A method and apparatus for granting access to a hardware interface shared between multiple software drivers are described. In one embodiment, the apparatus includes an interface to provide access to a hardware function or a resource. As described herein, the hardware function or resource is shared between at least two software entities, such as, for example, device drivers. In one embodiment, access verification logic denies an access request for the hardware function, unless the key associated with the access request matches a stored key semaphore. In one embodiment, a key size may be relatively large to provide a very low probability that a malicious software entity could accidentally or maliciously gain access to the software. Other embodiments are described and claimed.

Abstract: A method and apparatus for a race free data transfer algorithm using hardware based polling. One disclosed method transfers information between a target device and a buffer which is one of a set of buffers. The buffer is pointed to by a current buffer value stored in a controller. The current buffer value is adjusted to point to a next buffer if the current buffer value is different than a last buffer value. One of the set of buffers is serviced utilizing either the current buffer value or the last buffer value from the controller.

Abstract: According to one embodiment, an apparatus is presented. The apparatus includes a storage device, a hypervisor, a plurality of partitions mapped by the hypervisor, and a key created by the hypervisor to prevent one of the plurality of partitions from accessing a protected block range of the storage device. In one embodiment, a disk controller is coupled to the plurality of partitions to interface with the storage device, and the disk controller is programmed with the key in order to restrict access to the protected block range.

Abstract: In some embodiment, an arrangement is provided to prevent a loss of data in a memory due to a power failure for a computing system. When the power failure occurs, any pending memory write operations may be completed and dirty cache lines may be flushed back to the memory. Subsequently, the computing system may be put into a loss-prevention state, under which power may be turned off for all components in the computing system except the memory. The memory is powered by a battery pack which includes batteries and is in a self refresh state. When the power returns, applications and operating systems running in the computing system may resume what is left out when the power supply failure occurs, based at least in part on data retained in the memory. Other embodiments are described and claimed.

Abstract: According to one embodiment, computer system is disclosed. The computer system includes a central processing unit (CPU) having a first thread having first associated thread identification (ID) and a second thread having second associated thread ID. The computer system also includes a chipset coupled to receive access requests from the CPU and to examine a thread ID included with the access request to determine which thread is requesting access.

Abstract: An integrated circuit device, such as a processor initiates a transition to a first power management state. The device then receives a request to exit the first power management state and, in response exits the first power management state at the highest of a reference operating voltage, such as a minimum operating voltage, and a current voltage. For one aspect, an analog to digital converter may be used to determine the current voltage level. Further, for one aspect the first power management state may be a deeper sleep (C4) state, and the processor may quickly exit to a C2 state in response to a bus event such as a bus snoop.

Abstract: Systems and methods of managing power provide for receiving notification of a pending power state transition and using coordination hardware to determine whether the power state transition in a primary device is permitted by a set of secondary devices. In one embodiment, the primary device shares a resource with the set of secondary devices.

Abstract: Methods and apparatuses for coordination of power state management in and electronic system.

Abstract: In one embodiment, a design is described for providing the BIOS instructions to a computer through the USB port. At boot-up, a USB controller checks the USB port for a bootable device containing BIOS instructions. If a bootable device is connected, the USB controller transfers the BIOS instructions through the USB port to the processor. The computer then boots-up using the USB boot instructions. If no bootable device is connected to the USB port, the computer looks to a standard BIOS EPROM for boot instructions.

Abstract: Embodiments of methods and systems for improving boot-up time in computer systems utilize RAM in devices separate from the main memory, normally dedicated to another function, to provide a stack and temporary storage during BIOS execution, enabling BIOS to call subroutines and execute in a multi-threading fashion, speeding system boot-up.

Abstract: A docking architecture for a notebook computer is described. Specifically, a circuit coupled to a Low Pin Count (LPC) bus monitors the LPC bus for trusted data cycles. If a trusted data cycle is detected, the circuit prevents the trusted data cycle from being available to a non-trusted component.

Abstract: A protected configuration space is implemented as at least one range of memory addresses that are mapped to logic external to system memory. The memory addresses access logic that performs control and status operations pertaining to a protected operating environment. Some of the addresses may access protected configuration registers. Commands having destination addresses within the protected configuration space may not be completed if the commands are not issued by a processor, or if the commands are not part of a group of one or more designated protected commands. A separately addressable non-protected configuration space may also be implemented, accessible by processors, non-processors and/or non-protected commands.

Abstract: According to one embodiment, computer system is disclosed. The computer system includes a central processing unit (CPU), and a chipset coupled to the CPU including protected registers and a host controller. The computer system also includes a bus coupled to the host controller and a peripheral device coupled the bus. Trusted software accesses the protected registers to transmit encrypted data between the host controller and the peripheral device upon startup of the computer system to verify that the peripheral device is trustworthy.

Abstract: A method, apparatus, and article of manufacture for generating signals using a Universal Serial Bus (USB) host controller and USB keyboard. Data generated by the keyboard is marked as being used with an operating system which responds to keyboard generated interrupts and which reads keyboard data stored in a register. The marked data is detected after it is received from the keyboard and is transferred to a register. An interrupt to a central processing unit (CPU) is then generated in response to the marked data being transferred to the register.

Abstract: A system management interrupt (SMI) generation circuitry is provided to a universal serial bus (USB) complaint personal computer (PC) for generating a SMI whenever the USB controller attempts to generate a data-in interrupt received response to data in from a USB compatible keyboard/pointing device, and whenever an application attempts to perform a direct data-out to the AT keyboard controller. Additionally, a SMI handler is provided to service the SMIs, rerouting the data in to the appropriate input port of the AT keyboard controller, simulating receipt of data from an attached keyboard, thereby providing the data-in to the non-USB cognition application, and rerouting the data-out to the USB controller, thereby providing the data to the targeted USB keyboard/pointing device. As a result, compatibility is maintained between a USB compatible keyboard/pointing device, and non-USB cognition applications that perform direct data-in and data-out against the keyboard controllers.

Abstract: A method and apparatus for controlling accesses to DMA control registers, specifically operating according to a Distributed Direct Memory Access (DDMA) protocol. When an access to a peripheral device ends in a Master Abort due to the failure of the peripheral device to respond to the DDMA Master component during a DDMA transaction, a System Management Interrupt (SMI#) is generated to the central processing unit. In the resulting execution of the System Management Mode code by the CPU, the cause of the peripheral component not responding (e.g., that the peripheral is in a low power mode, the connection between the DDMA master and the peripheral is interrupted, etc.) is determined. The CPU, executing SMM code, takes steps to correct the problem. For example, if the peripheral is powered down, the CPU will power it up so that the DDMA transaction can subsequently occur.