Patents by Inventor David Questad
David Questad has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9508789Abstract: An electronic module includes a substrate including at least one structure that reduces stress flow through the substrate, wherein the structure includes at least one trench in a surface of the substrate, and a plurality of capacitor legs disposed on an upper surface of the substrate.Type: GrantFiled: January 17, 2014Date of Patent: November 29, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: David Questad, Vijayeshwar D Khanna, Jennifer V Muncy, Arun Sharma, Sri M Sri-Jayantha, Lorenzo Valdevit
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Publication number: 20140151849Abstract: An electronic module includes a substrate including at least one structure that reduces stress flow through the substrate, wherein the structure includes at least one trench in a surface of the substrate, and a plurality of capacitor legs disposed on an upper surface of the substrate.Type: ApplicationFiled: January 17, 2014Publication date: June 5, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David Questad, Vijayeshwar D. Khanna, Jennifer V. Muncy, Arun Sharma, Sri M. Sri-Jayantha, Lorenzo Valdevit
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Patent number: 8659119Abstract: An electronic module including a substrate having at least one structure that reduces stress flow through the substrate, wherein the structure comprises at least one trench in a surface of the substrate.Type: GrantFiled: May 20, 2010Date of Patent: February 25, 2014Assignee: International Business Machines CorporationInventors: Vijayeshwar D. Kharma, Jennifer V. Muncy, Arun Sharma, Sri M. Sri-Jayantha, Lorenzo Valdevit, David Questad
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Patent number: 8054630Abstract: A method of mounting an electronic component on a substrate includes forming at least one trench in a surface of the substrate. The trenches formed in the substrate reduce a stiffness of the substrate, which provides less resistance to shear. Accordingly, the trenches reduce the amount of strain on the joints, which mount the electronic component to the substrate, which enhances the life of the joints.Type: GrantFiled: February 13, 2008Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventors: David Questad, Vijayeshwar D. Khanna, Jennifer V. Muney, Arun Sharma, Sri M. Sri-Jayantha, Lorenzo Valdevit
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Patent number: 7855430Abstract: A method of mounting an electronic component on a substrate includes forming at least one trench in a surface of the substrate. The trenches formed in the substrate reduce a stiffness of the substrate, which provides less resistance to shear. Accordingly, the trenches reduce the amount of strain on the joints, which mount the electronic component to the substrate, which enhances the life of the joints.Type: GrantFiled: April 8, 2008Date of Patent: December 21, 2010Assignee: International Business Machines CorporationInventors: David Questad, Vijayeshwar D. Khanna, Jennifer V. Muncy, Arun Sharma, Sri M. Sri-Jayantha, Lorenzo Valdevit
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Publication number: 20100276784Abstract: An electronic module including a substrate having at least one structure that reduces stress flow through the substrate, wherein the structure comprises at least one trench in a surface of the substrate.Type: ApplicationFiled: May 20, 2010Publication date: November 4, 2010Applicant: International Business Machines CorporationInventors: David Questad, Vijayeshwar D. Kharma, Jennifer V. Muncy, Arun Sharma, Sri M. Sri-Jayantha, Lorenzo Valdevit
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Patent number: 7777301Abstract: A method of mounting an electronic component on a substrate includes forming at least one trench in a surface of the substrate. The trenches formed in the substrate reduce a stiffness of the substrate, which provides less resistance to shear. Accordingly, the trenches reduce the amount of strain on the joints, which mount the electronic component to the substrate, which enhances the life of the joints.Type: GrantFiled: April 8, 2008Date of Patent: August 17, 2010Assignee: International Business Machines CorporationInventors: David Questad, Vijayeshwar D. Khanna, Jennifer V. Muncy, Arun Sharma, Sri M. Sri-Jayantha, Lorenzo Valdevit
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Patent number: 7732894Abstract: A method of mounting an electronic component on a substrate includes forming at least one trench in a surface of the substrate. The trenches formed in the substrate reduce a stiffness of the substrate, which provides less resistance to shear. Accordingly, the trenches reduce the amount of strain on the joints, which mount the electronic component to the substrate, which enhances the life of the joints.Type: GrantFiled: February 13, 2008Date of Patent: June 8, 2010Assignee: International Business Machines CorporationInventors: David Questad, Vijayeshwar D. Khanna, Jennifer V. Muney, Arun Sharma, Sri M. Sri-Jayantha, Lorenzo Valdevit
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Publication number: 20090085161Abstract: A method of mounting an electronic component on a substrate includes forming at least one trench in a surface of the substrate. The trenches formed in the substrate reduce a stiffness of the substrate, which provides less resistance to shear. Accordingly, the trenches reduce the amount of strain on the joints, which mount the electronic component to the substrate, which enhances the life of the joints.Type: ApplicationFiled: February 13, 2008Publication date: April 2, 2009Applicant: International Business Machines CorporationInventors: David Questad, Vijayeshwar D. Khanna, Jennifer V. Muney, Arun Sharma, Sri M. Sri-Jayantha, Lorenzo Valdevit
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Publication number: 20080226875Abstract: A method of mounting an electronic component on a substrate includes forming at least one trench in a surface of the substrate. The trenches formed in the substrate reduce a stiffness of the substrate, which provides less resistance to shear. Accordingly, the trenches reduce the amount of strain on the joints, which mount the electronic component to the substrate, which enhances the life of the joints.Type: ApplicationFiled: April 8, 2008Publication date: September 18, 2008Applicant: International Business Machines CorporationInventors: David Questad, Vijayeshwar D. Khanna, Jennifer V. Muncy, Arun Sharma, Sri M. Sri-Jayantha, Lorenzo Valdevit
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Publication number: 20080218990Abstract: A method of mounting an electronic component on a substrate includes forming at least one trench in a surface of the substrate. The trenches formed in the substrate reduce a stiffness of the substrate, which provides less resistance to shear. Accordingly, the trenches reduce the amount of strain on the joints, which mount the electronic component to the substrate, which enhances the life of the joints.Type: ApplicationFiled: April 8, 2008Publication date: September 11, 2008Applicant: International Business Machines CorporationInventors: David Questad, Vijayeshwar D. Khanna, Jennifer V. Muncy, Arun Sharma, Sri M. Sri-Jayantha, Lorenzo Valdevit
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Publication number: 20080205023Abstract: A method of mounting an electronic component on a substrate includes forming at least one trench in a surface of the substrate. The trenches formed in the substrate reduce a stiffness of the substrate, which provides less resistance to shear. Accordingly, the trenches reduce the amount of strain on the joints, which mount the electronic component to the substrate, which enhances the life of the joints.Type: ApplicationFiled: February 27, 2007Publication date: August 28, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Vijayeshwar D. Khanna, Jennifer V. Muncy, Arun Sharma, Sri M. Sri-Jayantha, Lorenzo Valdevit, David Questad
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Publication number: 20080205024Abstract: A method of mounting an electronic component on a substrate includes forming at least one trench in a surface of the substrate. The trenches formed in the substrate reduce a stiffness of the substrate, which provides less resistance to shear. Accordingly, the trenches reduce the amount of strain on the joints, which mount the electronic component to the substrate, which enhances the life of the joints.Type: ApplicationFiled: February 13, 2008Publication date: August 28, 2008Applicant: International Business Machines CorporationInventors: David Questad, Vijayeshwar D. Khanna, Jennifer V. Muney, Arun Sharma, Sri M. Sri-Jayantha, Lorenzo Valdevit
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Patent number: 7329816Abstract: An electronic package and method of formation. A thermally conductive layer having first and second opposing surfaces is provided. A first dielectric layer is laminated under pressurization to the first opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T1MIN and a maximum temperature T1MAX. T1MAX constrains the ductility of the first dielectric layer to be at least D1 following the laminating. T1MAX depends on D1 and on a first dielectric material comprised by the first dielectric layer. A second dielectric layer is laminated under pressurization to the second opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T2MIN and a maximum temperature T2MAX. T2MAX constrains the ductility of the second dielectric layer to be at least D2 following the laminating. T2MAX depends on D2 and on a second dielectric material comprised by the second dielectric layer.Type: GrantFiled: June 8, 2005Date of Patent: February 12, 2008Assignee: International Business Machines CorporationInventors: Donald S. Farquhar, James D. Herard, Michael J. Klodowski, David Questad, Der-jin Woan
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Publication number: 20080022519Abstract: A laminating method. A structure that includes first and second dielectric layers respectively positioned on opposing surfaces of a thermally conductive layer is pressurized between 1000 and 3000 psi concurrent with being subjected to a thermal process, including the steps of: (a) heating the structure from ambient room temperature to a temperature between 670° F. to 695° F. in a heatup stage of duration 42 to 57 minutes; (b) after step (a), maintaining the structure at an approximately constant temperature between 670° F. and 695° F. in a dwell stage of duration 105 to 125 minutes; (c) after step (b), cooling the structure to 400° F. in a slow cool stage of duration of 120 to 150 minutes, wherein step (c) is performed after step (b); and (d) after step (3), cooling the structure to ambient room temperature in a rapid cool stage of duration less than 180 minutes.Type: ApplicationFiled: October 2, 2007Publication date: January 31, 2008Inventors: Donald Farquhar, James Herard, Michael Klodowski, David Questad, Der-jin Woan
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Publication number: 20070236890Abstract: Disclosed are thermally conductive plates. Each plate is configured such that a uniform adhesive-filled gap may be achieved between the plate and a heat generating structure when the plate is bonded to the heat generating structure and subjected to a temperature within a predetermined temperature range that causes the heat generating structure to warp. Additionally, this disclosure presents the associated methods of forming the plates and of bonding the plates to a heat generating structure. In one embodiment the plate is curved and modeled to match the curved surface of a heat generating structure within the predetermined temperature range. In another embodiment the plate is a multi-layer conductive structure that is configured to undergo the same warpage under a thermal load as the heat generating structure. Thus, when the plate is bonded with the heat generating structure it is able to achieve and maintain a uniform adhesive-filled gap at any temperature.Type: ApplicationFiled: June 5, 2007Publication date: October 11, 2007Inventors: Jeffrey Coffin, Michael Gaynes, David Questad, Kamal Sikka, Hilton Toy, Jamil Wakil
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Publication number: 20070200229Abstract: A semiconductor structure and method for forming the same. The semiconductor structure includes (a) a substrate and (b) a chip which includes N chip solder balls, N is a positive integer, and the N chip solder balls are in electrical contact with the substrate. The semiconductor structure further includes (c) first, second, third, and fourth corner underfill regions which are respectively at first, second, third, and fourth corners of the chip, and sandwiched between the chip and the substrate. The semiconductor structure further includes (d) a main underfill region sandwiched between the chip and the substrate. The first, second, third, and fourth corner underfill regions, and the main underfill region occupy essentially an entire space between the chip and the substrate. A corner underfill material of the first, second, third, and fourth corner underfill regions is different from a main underfill material of the main underfill region.Type: ApplicationFiled: February 27, 2006Publication date: August 30, 2007Inventors: Timothy Daubenspeck, Jeffrey Gambino, Christopher Muzzy, Wolfgang Sauter, David Questad
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Publication number: 20070023913Abstract: A circuit board comprises a resin-filled plated (RFP) through-hole; a dielectric layer over the RFP through-hole; a substantially circular RFP cap in the dielectric layer and connected to an upper opening of the RFP through-hole; a via stack in the dielectric layer; and a plurality of via lands extending radially outward from the via stack, wherein each of the plurality of via lands is diametrically larger than the RFP cap. Preferably, the RFP cap comprises a diameter of at least 300 ?m. Preferably, each of the via lands comprises a substantially circular shape having a diameter of at least 400 ?m. Moreover, the circuit board further comprises a ball grid array pad connected to the via stack; and input/output ball grid array pads connected to the ball grid array pad. Additionally, the circuit board further comprises metal planes in the dielectric layer.Type: ApplicationFiled: July 28, 2005Publication date: February 1, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jean Audet, Jon Casey, Luc Guerin, David Questad, David Russell
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Publication number: 20060268521Abstract: Disclosed are thermally conductive plates. Each plate is configured such that a uniform adhesive-filled gap may be achieved between the plate and a heat generating structure when the plate is bonded to the heat generating structure and subjected to a temperature within a predetermined temperature range that causes the heat generating structure to warp. Additionally, this disclosure presents the associated methods of forming the plates and of bonding the plates to a heat generating structure. In one embodiment the plate is curved and modeled to match the curved surface of a heat generating structure within the predetermined temperature range. In another embodiment the plate is a multi-layer conductive structure that is configured to undergo the same warpage under a thermal load as the heat generating structure. Thus, when the plate is bonded with the heat generating structure it is able to achieve and maintain a uniform adhesive-filled gap at any temperature.Type: ApplicationFiled: May 26, 2005Publication date: November 30, 2006Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jeffrey Coffin, Michael Gaynes, David Questad, Kamal Sikka, Hilton Toy, Jamil Wakil
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Patent number: 7059049Abstract: An electronic package and method of formation. A thermally conductive layer having first and second opposing surfaces is provided. A first dielectric layer is laminated under pressurization to the first opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T1MIN and a maximum temperature T1MAX. T1MAX constrains the ductility of the first dielectric layer to be at least D1 following the laminating. T1MAX depends on D1 and on a first dielectric material comprised by the first dielectric layer. A second dielectric layer is laminated under pressurization to the second opposing surface of the thermally conductive layer, at a temperature between a minimum temperature T2MIN and a maximum temperature T2MAX. T2MAX constrains the ductility of the second dielectric layer to be at least D2 following the laminating. T2MAX depends on D2 and on a second dielectric material comprised by the second dielectric layer.Type: GrantFiled: September 24, 2002Date of Patent: June 13, 2006Assignee: International Business Machines CorporationInventors: Donald S. Farquhar, James D. Herard, Michael J. Klodowski, David Questad, Der-jin Woan