Abstract: A multilayer substrate having a bonding surface is disclosed. One embodiment of the substrate may comprise a bypass capacitor connection pad disposed on the bonding surface. The bypass capacitor connection pad may have a bypass capacitor power pad and a bypass capacitor ground pad. The substrate may also comprise a plurality of power vias routed from the bypass capacitor power pad to a first redistribution layer spaced apart from the bonding surface and a plurality of ground vias routed from the bypass capacitor ground pad to the first redistribution layer. The substrate may further comprise a plurality of power and ground vias routed from the first redistribution layer to a second redistribution layer according to a power and ground via pattern array, wherein the plurality of ground vias are jogged at the first redistribution layer to the plurality of power vias to form the power and ground via pattern array.

Abstract: For a given channel and a filter having at least one filter tap, a set of at least one weight value is determined for the at least one filter tap according to which at least one weight value substantially minimizes a gradient of a frequency response for the given channel and substantially maximizes energy of the frequency response for the given channel within a predetermined bandwidth.

Abstract: Methods and apparatuses for affecting the frequency behavior of connections within a printed circuit board or an integrated circuit are disclosed. Some embodiments include a printed circuit board comprising, a plurality of conductive layers each comprising at least one conductive pad, where each conductive pad on the conductive layers includes a vacancy, and an insulating material disposed about the conductive layers such that the vacancies are at least partially filled with the insulating material.

Abstract: A method for routing vias in a multilayer substrate from bypass capacitor pads is disclosed. One embodiment of a method may comprise arranging a bypass capacitor power pad spaced apart from a bypass capacitor ground pad on a first surface of the multilayer substrate, routing a plurality of power vias from the bypass capacitor power pad to a first redistribution layer spaced from the first surface, and routing a plurality of ground vias from the bypass capacitor ground pad to the first redistribution layer. The methodology may further comprise jogging the plurality of ground vias at the first redistribution layer to the plurality of power vias to provide a power and ground via pattern, and routing the power and ground vias from the first redistribution layer to a second redistribution layer spaced apart from the first redistribution layer based on the power and ground via pattern.

Abstract: A method for routing vias in a multilayer substrate from bypass capacitor pads is disclosed. One embodiment of a method may comprise arranging a bypass capacitor power pad spaced apart from a bypass capacitor ground pad on a first surface of the multilayer substrate, routing a plurality of power vias from the bypass capacitor power pad to a first redistribution layer spaced from the first surface, and routing a plurality of ground vias from the bypass capacitor ground pad to the first redistribution layer. The methodology may further comprise jogging the plurality of ground vias at the first redistribution layer to the plurality of power vias to provide a power and ground via pattern, and routing the power and ground vias from the first redistribution layer to a second redistribution layer spaced apart from the first redistribution layer based on the power and ground via pattern.

Abstract: A method for routing vias in a multilayer substrate from bypass capacitor pads is disclosed. One embodiment of a method may comprise arranging a bypass capacitor power pad spaced apart from a bypass capacitor ground pad on a first surface of the multilayer substrate, routing a plurality of power vias from the bypass capacitor power pad to a first redistribution layer spaced from the first surface, and routing a plurality of ground vias from the bypass capacitor ground pad to the first redistribution layer. The methodology may further comprise jogging the plurality of ground vias at the first redistribution layer to the plurality of power vias to provide a power and ground via pattern, and routing the power and ground vias from the first redistribution layer to a second redistribution layer spaced apart from the first redistribution layer based on the power and ground via pattern.

Abstract: A method for verifying coupling in a differential trace pair group includes reading victim properties of a victim differential trace pair and culprit properties of a plurality of culprit differential trace pairs from a circuit design database. The method also includes calculating a plurality of coupling factors based on the victim properties and the culprit properties, one from each of the plurality of culprit differential trace pairs to the victim differential trace pair. The method also includes calculating a total coupling factor for the victim differential trace pair based on the plurality of coupling factors, and flagging the victim differential trace pair if the total coupling factor exceeds a total coupling threshold level.

Abstract: A method for calculating worst case coupling for a differential pair group includes identifying a victim differential pair and at least one culprit differential pair in the differential pair group, calculating a coupling factor between each of the culprit differential pairs and the victim differential pair, and summing the absolute value of each of the coupling factors to generate a worst case coupling factor.

Abstract: A method for verifying coupling in a differential via pair group includes identifying a differential via pair group in a design database and identifying a victim differential via pair in the differential via pair group. All other differential via pairs in the differential via pair group are identified as culprit differential pairs. The differential via pair group includes at least one culprit differential via pair. The method also includes obtaining a total coupling threshold level and calculating a total coupling factor for the victim differential via pair within the differential via pair group. The method also includes flagging the victim differential via pair if the calculated total coupling factor exceeds the total coupling threshold level.

Abstract: A method evaluates signal trace discontinuities in an electronic design of the type having one or more traces. The method includes the steps of formulating one or more trace discontinuity rules, processing the electronic design to determine whether the traces violate the trace discontinuity rules, and generating an indicator (e.g., a DRC) associated with the electronic design to identify violated trace discontinuity rules. Each level, each signal net, or a group of signal nets may be evaluated, for example, to ensure compliance with the trace discontinuity rules.

Abstract: A system for determining S-parameters of a network includes an S-parameter calculator that computes the S-parameters of the network based on waveform parameters determined through single port measurements at each of plural ports of the network.

Abstract: A system and method can be utilized to determine S-parameters of a network. In one embodiment, system comprises an S-parameter calculator that computes the S-parameters of the network based on waveform parameters determined from single port measurements. At least one of the single port measurements corresponds to measurements at one of the plural ports while a matched load is applied to at least another of the plural ports.

Abstract: Solid-state waveguide structures are disclosed to detect and/or encode very fast (picosecond) optical signals. The waveguides are appropriately configured to cause very fast signals to interact with interrogation or erasure pulses by a two photon absorption mechanism. The coincidence of the pulses in particular regions causes erasure and/or changes in the waveguide conductivity which can be measured conventionally by parallel circuitry.